18150034. Packaged Memory Device and Method simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)
Contents
Packaged Memory Device and Method
Organization Name
Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s)
Chung-Hao Tsai of Huatan Township (TW)
Wei-Ting Chen of Tainan City (TW)
Chuei-Tang Wang of Taichung City (TW)
Packaged Memory Device and Method - A simplified explanation of the abstract
This abstract first appeared for US patent application 18150034 titled 'Packaged Memory Device and Method
Simplified Explanation
The patent application describes packaged memory devices with memory devices hybrid bonded to logic devices. Here are the key points:
- Semiconductor device with a first memory die and a second memory cell electrically coupled to a first word line.
- First interconnect structure electrically coupled to the first word line.
- Circuitry die with a second interconnect structure, where a first conductive feature of the first interconnect structure is bonded to a second conductive feature of the second interconnect structure through metal-to-metal bonds.
- Word line driver electrically coupled to the first word line between the first memory cell and the second memory cell through the first and second interconnect structures.
Potential Applications
- High-performance computing
- Data storage systems
- Mobile devices
Problems Solved
- Improved memory device integration
- Enhanced data processing speed
- Increased memory capacity
Benefits
- Higher efficiency in data transfer
- Enhanced overall system performance
- Compact design for space-saving applications
Original Abstract Submitted
Packaged memory devices including memory devices hybrid bonded to logic devices and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first memory die including a first memory cell electrically coupled to a first word line; a second memory cell electrically coupled to the first word line; and a first interconnect structure electrically coupled to the first word line; a circuitry die including a second interconnect structure, a first conductive feature of the first interconnect structure being bonded to a second conductive feature of the second interconnect structure through metal-to-metal bonds; and a word line driver electrically coupled to the first word line between the first memory cell and the second memory cell, the word line driver being electrically coupled to the first word line through the first interconnect structure and the second interconnect structure.
