18149206. MEMORY DEVICES HAVING CELL OVER PERIPHERY STRUCTURE, MEMORY PACKAGES INCLUDING THE SAME, AND METHODS OF MANUFACTURING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)

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MEMORY DEVICES HAVING CELL OVER PERIPHERY STRUCTURE, MEMORY PACKAGES INCLUDING THE SAME, AND METHODS OF MANUFACTURING THE SAME

Organization Name

SAMSUNG ELECTRONICS CO., LTD.

Inventor(s)

Yonghyuk Choi of Suwon-si (KR)

Bongsoon Lim of Seoul (KR)

Hongsoo Jeon of Suwon-si (KR)

Jaeduk Yu of Seoul (KR)

MEMORY DEVICES HAVING CELL OVER PERIPHERY STRUCTURE, MEMORY PACKAGES INCLUDING THE SAME, AND METHODS OF MANUFACTURING THE SAME - A simplified explanation of the abstract

This abstract first appeared for US patent application 18149206 titled 'MEMORY DEVICES HAVING CELL OVER PERIPHERY STRUCTURE, MEMORY PACKAGES INCLUDING THE SAME, AND METHODS OF MANUFACTURING THE SAME

Simplified Explanation

The abstract describes a memory device that consists of two semiconductor layers. The first layer contains wordlines, bitlines, an upper substrate, and a memory cell array. The memory cell array includes memory blocks. The second layer includes a lower substrate and an address decoder. Each memory block has a core region with memory cells, a first extension region with wordline contacts, and a second extension region with an insulating mold structure. The second extension region has step zones and flat zones, with through-hole vias in the flat zone. The wordlines and address decoder are connected through these through-hole vias.

  • The memory device has two semiconductor layers, with the first layer containing wordlines, bitlines, an upper substrate, and a memory cell array.
  • The memory cell array consists of memory blocks, each having a core region with memory cells, a first extension region with wordline contacts, and a second extension region with an insulating mold structure.
  • The second extension region has step zones and flat zones, with through-hole vias present in the flat zone.
  • The wordlines and address decoder are electrically connected through these through-hole vias.

Potential Applications

  • This memory device can be used in various electronic devices that require high-density memory storage, such as smartphones, tablets, and computers.
  • It can also be utilized in data centers and servers to enhance data processing and storage capabilities.

Problems Solved

  • The memory device solves the problem of limited memory storage capacity by providing a high-density memory cell array.
  • It addresses the need for efficient electrical connections between wordlines and the address decoder through through-hole vias.

Benefits

  • The memory device offers increased memory storage capacity due to its high-density memory cell array.
  • It provides efficient electrical connections between wordlines and the address decoder, improving overall device performance.
  • The through-hole vias in the flat zone of the second extension region simplify the electrical connection process.


Original Abstract Submitted

A memory device includes first and second semiconductor layers. The first semiconductor layer includes wordlines and bitlines, an upper substrate, and a memory cell array. The memory cell array includes a memory blocks. The second semiconductor layer includes a lower substrate, and an address decoder. Each memory block includes a core region including a memory cells, a first extension region adjacent to a first side of the core region and including a plurality of wordline contacts, and a second extension region adjacent to a second side of the core region and including an insulating mold structure. The second extension region includes step zones and at least one flat zone. Through-hole vias penetrating the insulating mold structure are in the flat zone. The wordlines and the address decoder are electrically connected with each other by at least the through-hole vias.