17983145. SEMICONDUCTOR PACKAGE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)

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SEMICONDUCTOR PACKAGE

Organization Name

SAMSUNG ELECTRONICS CO., LTD.

Inventor(s)

Heungkyu Kwon of Suwon-si (KR)

Taewoo Kang of Suwon-si (KR)

Taehun Kim of Suwon-si (KR)

SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract

This abstract first appeared for US patent application 17983145 titled 'SEMICONDUCTOR PACKAGE

Simplified Explanation

The abstract describes a semiconductor package that includes a package substrate with three chip mounting areas spaced apart from each other. The package also includes semiconductor chips mounted on these areas, and two stiffeners mounted on the substrate to separate the chip mounting areas.

  • The semiconductor package has a package substrate with multiple chip mounting areas.
  • Semiconductor chips are mounted on these chip mounting areas.
  • Two stiffeners are used to separate the chip mounting areas from each other.

Potential applications of this technology:

  • Electronics manufacturing industry
  • Semiconductor packaging industry
  • Integrated circuit production

Problems solved by this technology:

  • Efficiently organizing and separating multiple semiconductor chips on a package substrate.
  • Preventing interference or damage between the chips.
  • Facilitating the manufacturing process of semiconductor packages.

Benefits of this technology:

  • Improved organization and arrangement of semiconductor chips.
  • Enhanced protection and reliability of the chips.
  • Streamlined manufacturing process for semiconductor packages.


Original Abstract Submitted

A semiconductor package includes a package substrate including a first chip mounting area, a second chip mounting area, and a third chip mounting area spaced apart from one another in a first direction, semiconductor chips mounted on the first to third chip mounting areas, a first stiffener mounted on the package substrate to separate the first chip mounting area from the second chip mounting area, and a second stiffener mounted on the package substrate to separate the second chip mounting area from the third chip mounting area.