17956753. DYNAMIC RANDOM-ACCESS MEMORY IN A MOLDING BENEATH A DIE simplified abstract (Intel Corporation)
Contents
- 1 DYNAMIC RANDOM-ACCESS MEMORY IN A MOLDING BENEATH A DIE
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 DYNAMIC RANDOM-ACCESS MEMORY IN A MOLDING BENEATH A DIE - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
DYNAMIC RANDOM-ACCESS MEMORY IN A MOLDING BENEATH A DIE
Organization Name
Inventor(s)
Eng Huat Goh of Ayer Itam (MY)
Hazwani Jaffar of Kepala Batas (MY)
DYNAMIC RANDOM-ACCESS MEMORY IN A MOLDING BENEATH A DIE - A simplified explanation of the abstract
This abstract first appeared for US patent application 17956753 titled 'DYNAMIC RANDOM-ACCESS MEMORY IN A MOLDING BENEATH A DIE
Simplified Explanation
Embodiments herein relate to systems, apparatuses, or processes directed to a package that includes a die, which may be a processor die, coupled with a first side of a substrate and one or more dies, which may be one or more memory dies, that are coupled with a second side of the substrate opposite the first side of the substrate. All or part of the memory dies may be directly below the die with respect to a plane of the substrate and may be partially or completely within a molding. Other embodiments may be described and/or claimed.
- Package includes a processor die and one or more memory dies on opposite sides of a substrate.
- Memory dies may be positioned directly below the processor die within a molding.
Potential Applications
This technology could be applied in:
- High-performance computing systems
- Data centers for efficient memory management
Problems Solved
- Efficient memory integration in a compact package
- Improved thermal management for dies
Benefits
- Enhanced performance due to close proximity of processor and memory dies
- Space-saving design for compact electronic devices
Potential Commercial Applications
Optimizing memory integration in:
- Smartphones and tablets
- Laptops and ultrabooks
Possible Prior Art
Prior art may include:
- Existing packaging technologies for processor and memory dies
- Molding techniques for semiconductor devices
Unanswered Questions
How does this technology impact power consumption in electronic devices?
The article does not delve into the power efficiency of the package design.
Are there any limitations to the size or type of dies that can be integrated using this packaging method?
The article does not address any restrictions on die size or compatibility with different types of dies.
Original Abstract Submitted
Embodiments herein relate to systems, apparatuses, or processes directed to a package that includes a die, which may be a processor die, coupled with a first side of a substrate and one or more dies, which may be one or more memory dies, that are coupled with a second side of the substrate opposite the first side of the substrate. All or part of the memory dies may be directly below the die with respect to a plane of the substrate and may be partially or completely within a molding. Other embodiments may be described and/or claimed.
