17948521. Memory Circuitry And Method Used In Forming Memory Circuitry simplified abstract (Micron Technology, Inc.)
Contents
- 1 Memory Circuitry And Method Used In Forming Memory Circuitry
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 Memory Circuitry And Method Used In Forming Memory Circuitry - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
Memory Circuitry And Method Used In Forming Memory Circuitry
Organization Name
Inventor(s)
Sidhartha Gupta of Boise ID (US)
Adam W. Saxler of Boise ID (US)
Memory Circuitry And Method Used In Forming Memory Circuitry - A simplified explanation of the abstract
This abstract first appeared for US patent application 17948521 titled 'Memory Circuitry And Method Used In Forming Memory Circuitry
Simplified Explanation
The memory array in this patent application comprises strings of memory cells with laterally-spaced memory blocks, each consisting of a vertical stack of insulative and conductive tiers above a conductor tier. Channel-material strings extend through the insulative and conductive tiers in the memory blocks, directly electrically coupling to the conductor material. Intervening material is present between the memory blocks, including a laterally-outer insulative lining and laterally-inner insulating material. An interface exists between the outer insulative lining and the inner insulating material.
- Memory array comprises strings of memory cells with memory blocks
- Memory blocks have vertical stacks of insulative and conductive tiers
- Channel-material strings extend through insulative and conductive tiers
- Intervening material includes outer insulative lining and inner insulating material
- Interface between outer insulative lining and inner insulating material
Potential Applications
This technology could be applied in:
- High-density memory storage devices
- Advanced computing systems
- Data centers
Problems Solved
This technology helps to:
- Increase memory array density
- Improve data transfer speeds
- Enhance overall system performance
Benefits
The benefits of this technology include:
- Efficient use of space
- Faster data access
- Enhanced reliability and durability
Potential Commercial Applications
This technology could be commercially applied in:
- Semiconductor manufacturing
- Electronics industry
- Information technology sector
Possible Prior Art
One possible prior art for this technology could be:
- Memory arrays with vertical stacking of memory blocks
Unanswered Questions
How does this technology compare to existing memory array designs?
This article does not provide a direct comparison to existing memory array designs, leaving the reader to wonder about the specific advantages and disadvantages of this innovation.
What are the potential limitations or challenges in implementing this technology?
The article does not address any potential limitations or challenges that may arise in implementing this technology, leaving room for further exploration into its practical applications and feasibility.
Original Abstract Submitted
A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers in the memory blocks. The channel-material strings directly electrically couple to conductor material of the conductor tier. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises a laterally-outer insulative lining extending longitudinally-along the immediately-laterally-adjacent memory-blocks. The laterally-outer insulative lining has its lowest surface between a top and a bottom of the lowest conductive tier. The laterally-outer insulative lining has its highest surface at or below a lowest surface of the next-lowest conductive tier. Laterally-inner insulating material extends longitudinally-along the immediately-laterally-adjacent memory blocks laterally-inward of the laterally-outer insulative lining. An interface is between the laterally-outer insulative lining and the laterally-inner insulating material. Methods are also disclosed.
