17945448. SUPPORT PILLARS WITH MULTIPLE, ALTERNATING EPITAXIAL SILICON FOR HORIZONTAL ACCESS DEVICES IN VERTICAL simplified abstract (Micron Technology, Inc.)
Contents
- 1 SUPPORT PILLARS WITH MULTIPLE, ALTERNATING EPITAXIAL SILICON FOR HORIZONTAL ACCESS DEVICES IN VERTICAL
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 SUPPORT PILLARS WITH MULTIPLE, ALTERNATING EPITAXIAL SILICON FOR HORIZONTAL ACCESS DEVICES IN VERTICAL - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
SUPPORT PILLARS WITH MULTIPLE, ALTERNATING EPITAXIAL SILICON FOR HORIZONTAL ACCESS DEVICES IN VERTICAL
Organization Name
Inventor(s)
David K. Hwang of Boise ID (US)
Yoshitaka Nakamura of Boise ID (US)
Scott E. Sills of Boise ID (US)
Glen H. Walters of Boise ID (US)
SUPPORT PILLARS WITH MULTIPLE, ALTERNATING EPITAXIAL SILICON FOR HORIZONTAL ACCESS DEVICES IN VERTICAL - A simplified explanation of the abstract
This abstract first appeared for US patent application 17945448 titled 'SUPPORT PILLARS WITH MULTIPLE, ALTERNATING EPITAXIAL SILICON FOR HORIZONTAL ACCESS DEVICES IN VERTICAL
Simplified Explanation
The abstract describes a patent application for vertically stacked memory cells with horizontally oriented access devices and storage nodes formed in tiers using silicon germanium (SiGe) and single crystalline silicon (Si).
- Silicon germanium (SiGe) and single crystalline silicon (Si) are used in different thicknesses to form tiers in vertically stacked memory cells.
- The horizontally oriented access devices have first and second source/drain regions separated by single crystalline silicon (Si) channel regions.
- Dielectric material is included in the single crystalline silicon (Si) channel regions to provide support structure for the horizontal access devices in vertical three-dimensional (3D) memory.
- Horizontally oriented access lines connect to gate structures opposing the channel regions, with vertical digit lines coupled to the first source/drain regions.
Potential Applications
This technology could be applied in:
- High-density memory storage devices
- Advanced computing systems
Problems Solved
This technology addresses:
- Increasing demand for higher memory storage capacity
- Need for more efficient and compact memory solutions
Benefits
The benefits of this technology include:
- Improved memory storage density
- Enhanced performance and speed of memory access
Potential Commercial Applications
This technology has potential commercial applications in:
- Data centers
- Consumer electronics
Possible Prior Art
One possible prior art for this technology could be the use of silicon germanium (SiGe) and single crystalline silicon (Si) in memory devices, but the specific configuration and structure described in the patent application may be novel.
Unanswered Questions
How does the use of silicon germanium (SiGe) and single crystalline silicon (Si) impact the overall performance of the memory cells?
The abstract mentions the use of these materials in different thicknesses, but it does not provide specific details on how this impacts the performance of the memory cells.
Are there any limitations or drawbacks to using this technology in memory devices?
While the abstract highlights the benefits of this technology, it does not mention any potential limitations or drawbacks that may be associated with its implementation.
Original Abstract Submitted
Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes formed in tiers. And, more particularly, to multiple, alternating silicon germanium (SiGe) and single crystalline silicon (Si) in different thicknesses to form tiers in which to form the horizontal access devices in vertical three-dimensional (3D) memory. The horizontally oriented access devices can have a first source/drain regions and a second source drain regions separated by single crystalline silicon (Si) channel regions. The single crystalline silicon (Si) channel regions can include a dielectric material to provide support structure to the single crystalline channel regions when forming the horizontal access devices in vertical three-dimensional (3D) memory. Horizontally oriented access lines can connect to gate structures opposing the channel regions. Vertical digit lines coupled to the first source/drain regions.
