17943706. BUILT-IN SELF-TEST BURST PATTERNS BASED ON ARCHITECTURE OF MEMORY simplified abstract (Micron Technology, Inc.)
Contents
- 1 BUILT-IN SELF-TEST BURST PATTERNS BASED ON ARCHITECTURE OF MEMORY
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 BUILT-IN SELF-TEST BURST PATTERNS BASED ON ARCHITECTURE OF MEMORY - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Original Abstract Submitted
BUILT-IN SELF-TEST BURST PATTERNS BASED ON ARCHITECTURE OF MEMORY
Organization Name
Inventor(s)
Daniele Balluchi of Cernusco Sul Naviglio (IT)
Chad B. Erickson of Boise ID (US)
Danilo Caraccio of Milano (IT)
BUILT-IN SELF-TEST BURST PATTERNS BASED ON ARCHITECTURE OF MEMORY - A simplified explanation of the abstract
This abstract first appeared for US patent application 17943706 titled 'BUILT-IN SELF-TEST BURST PATTERNS BASED ON ARCHITECTURE OF MEMORY
Simplified Explanation
The abstract of the patent application describes methods, systems, and devices related to built-in self-test burst patterns based on the architecture of memory. A controller is coupled to a memory device, with the controller including built-in self-test (BIST) circuitry. The BIST circuitry includes registers configured to store write burst patterns and read burst patterns based on the memory device's architecture.
- The patent application focuses on built-in self-test burst patterns for memory devices.
- The controller is equipped with BIST circuitry to facilitate self-testing.
- The BIST circuitry stores write burst patterns and read burst patterns in registers.
- The patterns are based on the memory device's architecture.
Potential Applications
This technology can be applied in:
- Memory testing and validation processes.
- Quality control in memory manufacturing.
- Error detection and correction in memory systems.
Problems Solved
- Ensures the reliability and functionality of memory devices.
- Streamlines the testing process for memory components.
- Facilitates early detection of memory-related issues.
Benefits
- Improved performance and reliability of memory devices.
- Cost-effective testing and validation procedures.
- Enhanced overall quality of memory products.
Potential Commercial Applications
Optimized for:
- Memory chip manufacturers.
- Computer hardware companies.
- Data center operators.
Possible Prior Art
There are existing methods for memory testing and validation, but the specific approach of using built-in self-test burst patterns based on memory architecture may be novel.
Unanswered Questions
How does this technology compare to traditional memory testing methods?
This article does not provide a direct comparison between the proposed technology and traditional memory testing methods.
What impact could this technology have on the memory industry as a whole?
The potential industry-wide implications of implementing this technology are not discussed in the article.
Original Abstract Submitted
Methods, systems, and devices related to built-in self-test burst patterns based on architecture of memory. A controller can be coupled to a memory device. The controller can include built-in self-test (BIST) circuitry. The BIST circuitry can include registers configured to store respective write burst patterns and read burst patterns based on an architecture of the memory device.
