17942977. READ LEVEL COMPENSATION FOR PARTIALLY PROGRAMMED BLOCKS OF MEMORY DEVICES simplified abstract (Micron Technology, Inc.)
Contents
- 1 READ LEVEL COMPENSATION FOR PARTIALLY PROGRAMMED BLOCKS OF MEMORY DEVICES
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 READ LEVEL COMPENSATION FOR PARTIALLY PROGRAMMED BLOCKS OF MEMORY DEVICES - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Unanswered Questions
- 1.10 Original Abstract Submitted
READ LEVEL COMPENSATION FOR PARTIALLY PROGRAMMED BLOCKS OF MEMORY DEVICES
Organization Name
Inventor(s)
Nagendra Prasad Ganesh Rao of Folsom CA (US)
Paing Z. Htet of Union City CA (US)
Sead Zildzic, Jr. of Folsom CA (US)
Thomas Fiala of Folsom CA (US)
Jian Huang of Union City CA (US)
Zhenming Zhou of San Jose CA (US)
READ LEVEL COMPENSATION FOR PARTIALLY PROGRAMMED BLOCKS OF MEMORY DEVICES - A simplified explanation of the abstract
This abstract first appeared for US patent application 17942977 titled 'READ LEVEL COMPENSATION FOR PARTIALLY PROGRAMMED BLOCKS OF MEMORY DEVICES
Simplified Explanation
The patent application describes a system that includes a memory device with blocks made up of wordlines connected to memory cells, and a processing device that performs operations based on the state of these blocks.
- The system can determine a metric reflecting the number of programmed wordlines in a specified block.
- If the block is partially programmed, the system identifies a read voltage offset based on the metric.
- Using the read voltage offset, the system performs a read operation in response to a read request.
Potential Applications
This technology could be applied in the development of more efficient and reliable memory devices for various electronic devices, such as smartphones, computers, and servers.
Problems Solved
This technology helps in efficiently reading data from partially programmed memory blocks, improving the overall performance and reliability of memory devices.
Benefits
The system allows for more accurate and efficient read operations on memory blocks, leading to improved data retrieval and overall system performance.
Potential Commercial Applications
- Enhancing the performance of memory devices in consumer electronics
- Improving the reliability of memory storage in data centers
Unanswered Questions
How does this technology impact the power consumption of memory devices?
The article does not provide information on the power consumption implications of this technology.
Are there any limitations to the size or type of memory blocks that can be used with this system?
The article does not address any potential limitations regarding the size or type of memory blocks compatible with this technology.
Original Abstract Submitted
A system can include a memory device containing blocks made up of wordlines respectively connected to sets of memory cells, and a processing device, operatively coupled with the memory device to perform operations including responsive to receiving a read request that specifies a block, determining a value of a metric reflective of a number of programmed wordlines of the block. The operations can also include responsive to determining, based on the value of the metric, that the block is in a partially programmed state, identifying a read voltage offset corresponding to the value of the metric, and performing, using the read voltage offset, a read operation responsive to the read request.
