17899550. WIRE BONDING DIRECTLY ON EXPOSED CONDUCTIVE VIAS AND INTERCONNECTS AND RELATED SYSTEMS AND METHODS simplified abstract (Micron Technology, Inc.)
Contents
WIRE BONDING DIRECTLY ON EXPOSED CONDUCTIVE VIAS AND INTERCONNECTS AND RELATED SYSTEMS AND METHODS
Organization Name
Inventor(s)
Kelvin Tan Aik Boo of Singapore (SG)
See Hiong Leow of Singapore (SG)
WIRE BONDING DIRECTLY ON EXPOSED CONDUCTIVE VIAS AND INTERCONNECTS AND RELATED SYSTEMS AND METHODS - A simplified explanation of the abstract
This abstract first appeared for US patent application 17899550 titled 'WIRE BONDING DIRECTLY ON EXPOSED CONDUCTIVE VIAS AND INTERCONNECTS AND RELATED SYSTEMS AND METHODS
Simplified Explanation
The patent application discloses stacked semiconductor devices with a package substrate, interconnect, stack of dies, and wirebonds.
- Package substrate has at least a first layer and a second layer with frustoconical shaped sections of the interconnect.
- Sections of the package substrate are directly coupled together.
- Uppermost layer of the package substrate has an exposed section at the upper surface for wirebond coupling.
- Potential Applications:**
- High-density integrated circuits
- Memory modules
- Microprocessors
- Problems Solved:**
- Increased packaging density
- Enhanced electrical connectivity
- Improved thermal management
- Benefits:**
- Compact design
- Efficient signal transmission
- Enhanced performance and reliability
Original Abstract Submitted
Stacked semiconductor devices, and related systems and methods, are disclosed herein. In some embodiments, the stacked semiconductor device includes a package substrate having at least a first layer and a second layer, an interconnect extending through the package substrate, a stack of dies carried by the package substrate, and one or more wirebonds electrically coupling the stack of dies to package substrate. Each of the layers of the package substrate can include a section of the interconnect with a frustoconical shape. Each of the sections can be directly coupled together. Further, the section in an uppermost layer of the package substrate is exposed at an upper surface of the package substrate. The wirebonds can be directly coupled to the exposed surface of the uppermost section.
