17899531. MEMORY DEVICE WITH EMBEDDED DEEP LEARNING ACCELERATOR IN MULTI-CLIENT ENVIRONMENT simplified abstract (Micron Technology, Inc.)

MEMORY DEVICE WITH EMBEDDED DEEP LEARNING ACCELERATOR IN MULTI-CLIENT ENVIRONMENT

Organization Name

Micron Technology, Inc.

Inventor(s)

Dmitri Yudanov of Rancho Cordova CA (US)

Troy Allen Manning of Meridian ID (US)

MEMORY DEVICE WITH EMBEDDED DEEP LEARNING ACCELERATOR IN MULTI-CLIENT ENVIRONMENT - A simplified explanation of the abstract

This abstract first appeared for US patent application 17899531 titled 'MEMORY DEVICE WITH EMBEDDED DEEP LEARNING ACCELERATOR IN MULTI-CLIENT ENVIRONMENT

Simplified Explanation

- Memory device stores data from host device - Memory device includes memory interface to host device - Processing devices perform computations for neural network using data from memories - Output of neural network stored in memory - Controller manages memory access to avoid conflicts - Communication with host device using DRAM bus protocol, including sending neural network output

Potential Applications

- Artificial intelligence - Machine learning - Data processing

Problems Solved

- Efficient memory access - Avoiding conflicts in memory usage - Streamlining communication between devices

Benefits

- Faster data processing - Improved memory management - Enhanced performance in neural network computations

Original Abstract Submitted

Systems, methods, and apparatus related to memory devices. In one approach, a memory device includes memories that store data received from a host device. The memory device includes a memory interface to the host device. The memory device further includes one or more processing devices to perform, using a portion of the data stored in one or more of the memories, computations for a neural network. An output of the neural network is stored in one of the memories. The memory device has a controller that controls memory access by the host device and the processing devices to avoid a conflict. The memory device communicates with the host device over the memory interface using a DRAM bus protocol. This communication includes sending the output of the neural network to the host device.