17899305. ROW ADDRESS LATCHING FOR MULTIPLE ACTIVATE COMMAND PROTOCOL simplified abstract (Micron Technology, Inc.)
ROW ADDRESS LATCHING FOR MULTIPLE ACTIVATE COMMAND PROTOCOL
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Inventor(s)
ROW ADDRESS LATCHING FOR MULTIPLE ACTIVATE COMMAND PROTOCOL - A simplified explanation of the abstract
This abstract first appeared for US patent application 17899305 titled 'ROW ADDRESS LATCHING FOR MULTIPLE ACTIVATE COMMAND PROTOCOL
Simplified Explanation
- Memory device receives first activate command indicating first set of bits of a row address - Memory device stores first set of bits to obtain first delayed signal of the first set of bits - Memory device receives second activate command indicating second set of bits of the row address - Memory device stores second set of bits to obtain first delayed signal of the second set of bits - Memory device stores first delayed signal of the first set of bits to obtain second delayed signal of the first set of bits - Memory device activates a page of memory addressed according to the second delayed signal and the first delayed signal of the second set of bits
Potential Applications
- Memory devices - Computer systems - Data storage systems
Problems Solved
- Efficient row address latching for multiple activate command protocol - Improved memory access speed - Enhanced memory management
Benefits
- Faster memory access - Improved memory performance - Enhanced data processing capabilities
Original Abstract Submitted
Methods, systems, and devices for row address latching for multiple activate command protocol are described. A memory device may receive a first activate command that indicates a first set of bits of a row address and may store the first set of bits to obtain a first delayed signal of the first set of bits. The memory device may receive a second activate command that indicates a second set of bits of the row address and may store the second set of bits to obtain a first delayed signal of the second set of bits. The memory device may store the first delayed signal of the first set of bits to obtain a second delayed signal of the first set of bits and may activate a page of memory addressed according to the second delayed signal and the first delayed signal of the second set of bits.
