17899222. TRIPLE ACTIVATE COMMAND ROW ADDRESS LATCHING simplified abstract (Micron Technology, Inc.)
Contents
TRIPLE ACTIVATE COMMAND ROW ADDRESS LATCHING
Organization Name
Inventor(s)
Miki Matsumoto of Boise ID (US)
Kevin J. Ryan of Elizabeth CO (US)
TRIPLE ACTIVATE COMMAND ROW ADDRESS LATCHING - A simplified explanation of the abstract
This abstract first appeared for US patent application 17899222 titled 'TRIPLE ACTIVATE COMMAND ROW ADDRESS LATCHING
Simplified Explanation
- Memory device receives three activate commands for different sets of row address bits - Memory device activates a page of memory based on all three activate commands - Page of memory is addressed using the three sets of row address bits
Potential Applications
- Memory devices in computers
- Solid-state drives
- Mobile devices
Problems Solved
- Efficiently accessing specific pages of memory
- Reducing latency in memory access
Benefits
- Improved memory access speed
- Enhanced overall system performance
- Optimal utilization of memory resources
Original Abstract Submitted
Methods, systems, and devices for triple activate command row address latching are described. For instance, a memory device may receive a first activate command that indicates a first set of bits of a row address, a second activate command that indicates a second set of bits of the row address, and a third activate command that indicates a third set of bits of the row address. The memory device may activate a page of memory based on receiving the first activate command, the second activate command, and the third activate command, where the page of memory is addressed according to the first set of bits, the second set of bits, and the third set of bits.
