17898392. DRIFT CORRECTION IN SLC AND MLC MEMORY DEVICES simplified abstract (Micron Technology, Inc.)

DRIFT CORRECTION IN SLC AND MLC MEMORY DEVICES

Organization Name

Micron Technology, Inc.

Inventor(s)

Christophe Vincent Antoine Laurent of Agrate Brianza (MB) (IT)

Francesco Mastroianni of Melzo (MI) (IT)

Andrea Martinelli of Bergamo (BG) (IT)

Efrem Bolandrina of Fiorano al Serio (BG) (IT)

Lucia Di Martino of Monza (MB) (IT)

Riccardo Muzzetto of Arcore (MB) (IT)

Zhongyuan Lu of Boise ID (US)

Karthik Sarpatwari of Boise ID (US)

Nevil N. Gajera of Meridian ID (US)

DRIFT CORRECTION IN SLC AND MLC MEMORY DEVICES - A simplified explanation of the abstract

This abstract first appeared for US patent application 17898392 titled 'DRIFT CORRECTION IN SLC AND MLC MEMORY DEVICES

Simplified Explanation

- Techniques for correcting drift accumulation in memory cells - Memory device includes memory array with set of memory cells and memory controller - Memory controller reads data from memory array - Memory controller senses first distribution of memory cells, detects missing cell, increases voltage on missing cell to be read as part of first distribution - Detects second memory cell in second distribution was read while sensing first distribution - Masks second memory cell and marks it as belonging to second distribution

Potential Applications

- Memory devices - Data storage systems - Electronic devices requiring memory management

Problems Solved

- Correcting drift accumulation in memory cells - Ensuring accurate data reading from memory array - Preventing errors in memory cell sensing

Benefits

- Improved data reliability - Enhanced memory cell performance - Efficient memory management techniques

Original Abstract Submitted

Disclosed are techniques for correcting drift accumulation in memory cells. In some aspects, the techniques described herein relate to a memory device including: a memory array, the memory array including a set of memory cells; and a memory controller configured to read data from the memory array, the memory controller configured to: sense a first distribution of the set of memory cells, detect a missing cell in the first distribution, increase a voltage on the missing cell causing the missing cell to be read as part of the first distribution, detect that a second memory cell in a second distribution was read while sensing the first distribution, and mask the second memory cell and mark the second memory cell as belonging to the second distribution.