17898232. MEMORY DEVICES HAVING ONE-TIME-PROGRAMMABLE FUSES AND/OR ANTIFUSES FORMED FROM THIN-FILM TRANSISTORS simplified abstract (Micron Technology, Inc.)
MEMORY DEVICES HAVING ONE-TIME-PROGRAMMABLE FUSES AND/OR ANTIFUSES FORMED FROM THIN-FILM TRANSISTORS
Organization Name
Inventor(s)
Paolo Fantini of Vimercate (IT)
Fabio Pellizzer of Boise ID (US)
MEMORY DEVICES HAVING ONE-TIME-PROGRAMMABLE FUSES AND/OR ANTIFUSES FORMED FROM THIN-FILM TRANSISTORS - A simplified explanation of the abstract
This abstract first appeared for US patent application 17898232 titled 'MEMORY DEVICES HAVING ONE-TIME-PROGRAMMABLE FUSES AND/OR ANTIFUSES FORMED FROM THIN-FILM TRANSISTORS
Simplified Explanation
The abstract describes a memory device with a fuse array positioned in the insulative layer, configured as a non-volatile memory that can store trimming and other factors.
- Memory device with a fuse array for non-volatile memory storage
- Fuse array comprises transistors configured as fuses with different resistances representing logic states
- First subset of transistors have lower resistance for first logic state, second subset have higher resistance for second logic state
- Potential Applications:**
- Embedded systems
- Consumer electronics
- Automotive industry
- Industrial automation
- Problems Solved:**
- Non-volatile memory storage
- Efficient trimming and configuration storage
- Reliable memory device operation
- Benefits:**
- Enhanced memory device reliability
- Efficient storage of trimming and configuration data
- Versatile applications in various industries
Original Abstract Submitted
Memory devices, and associated systems and methods, are disclosed herein. A representative memory device comprises a substrate, an insulative layer over the substrate, and a memory array over the insulative layer. The memory device further comprises a fuse array positioned in the insulative layer and configured as a non-volatile memory that can store trimming and/or other factors. The fuse array can comprise a plurality of transistors configured as fuses and each including a source, a drain, and a gate. The transistors in a first subset of the transistors have a first resistance across one of the source, the drain, and the gate that represents a first logic state, and the transistors in a second subset of the transistors can have a second resistance across the one of the source, the drain, and the gate that is greater than the first resistance and that represents a second logic state.
