17898160. ACCESSING MEMORY DEVICES VIA SWITCHABLE CHANNELS simplified abstract (Micron Technology, Inc.)

ACCESSING MEMORY DEVICES VIA SWITCHABLE CHANNELS

Organization Name

Micron Technology, Inc.

Inventor(s)

Chulbum Kim of San Jose CA (US)

Sundararajan Sankaranarayanan of Fremont CA (US)

Xiangyu Tang of Mountain View CA (US)

Dustin J. Carter of Placerville CA (US)

ACCESSING MEMORY DEVICES VIA SWITCHABLE CHANNELS - A simplified explanation of the abstract

This abstract first appeared for US patent application 17898160 titled 'ACCESSING MEMORY DEVICES VIA SWITCHABLE CHANNELS

Simplified Explanation

The memory sub-system described in the patent application includes a memory sub-system controller with multiple controller channels, memory devices with multiple memory dies, and a channel switch circuit connecting the controller channels to the memory channels of the memory devices.

• The memory sub-system controller manages data flow between the controller channels and memory channels.
• Each memory channel corresponds to a specific memory die within a memory device.
• The channel switch circuit receives channel mappings from the controller, which specify the relationship between controller channels and memory channels.
• Data from each controller channel is routed to the corresponding memory channel based on the channel mappings.

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1. 1. 1. Potential Applications

• High-performance computing systems
• Data centers
• Artificial intelligence and machine learning applications

1. 1. 1. Problems Solved

• Efficient data transfer between memory controller and memory devices
• Optimized memory access for improved system performance

1. 1. 1. Benefits

• Increased data transfer speeds
• Enhanced memory management capabilities
• Improved overall system efficiency

Original Abstract Submitted

A memory sub-system includes a memory sub-system controller comprising a plurality of controller channels, one or more memory devices, each of which comprises a respective plurality of memory dies, and a channel switch circuit coupled between the plurality of the controller channels and a plurality of memory channels of the one or more memory devices, where each memory channel corresponds to a respective one of the plurality of memory dies of one of the memory devices, the channel switch circuit comprising command processing logic configured to: receive, from the memory sub-system controller, a plurality of channel mappings, each of which identifies a particular one of the controller channels and a particular one of the memory channels, and route data from each controller channel to a respective one of the memory channels that is associated with the controller channel by a respective one of the channel mappings.