17897910. AUTOMATED OPTIMIZATION OF ERROR-HANDLING FLOWS IN MEMORY DEVICES simplified abstract (Micron Technology, Inc.)
Contents
AUTOMATED OPTIMIZATION OF ERROR-HANDLING FLOWS IN MEMORY DEVICES
Organization Name
Inventor(s)
Jay Sarkar of San Jose CA (US)
Ipsita Ghosh of New Garia (IN)
Vamsi Pavan Rayaprolu of Santa Clara CA (US)
AUTOMATED OPTIMIZATION OF ERROR-HANDLING FLOWS IN MEMORY DEVICES - A simplified explanation of the abstract
This abstract first appeared for US patent application 17897910 titled 'AUTOMATED OPTIMIZATION OF ERROR-HANDLING FLOWS IN MEMORY DEVICES
Simplified Explanation
The patent application describes a system and method for optimizing error-handling operations performed on data in a memory device.
- Memory and processing device are connected.
- Processing device receives log data on error-handling operations.
- Optimization model based on error recovery probability and latency data is applied to the log data.
- Output of the optimization model provides a revised order of error-handling operations.
- Potential Applications
- Data storage systems
- Computer memory management
- Error detection and correction systems
- Problems Solved
- Efficient error-handling operations
- Improved data reliability
- Enhanced system performance
- Benefits
- Increased data integrity
- Faster error recovery
- Optimized memory management
Original Abstract Submitted
Systems and methods are disclosed including a memory and a processing device operatively coupled to the memory. The processing device can perform operations including receiving log data related to a first order of a set of error-handling operations performed on data residing in a segment of a memory device; applying an optimization model to the log data, wherein the optimization model is based on probability data of error recovery and latency data of the set of error-handling operations; and responsive to applying the optimization model to the log data, obtaining, as an output of the optimization model, a second order of the set of error-handling operations, wherein the second order adjusts an order of one or more error-handling operations of the set of error-handling operations in the first order.
