17897441. MANAGING DEFECTIVE BLOCKS DURING MULTI-PLANE PROGRAMMING OPERATIONS IN MEMORY DEVICES simplified abstract (Micron Technology, Inc.)
MANAGING DEFECTIVE BLOCKS DURING MULTI-PLANE PROGRAMMING OPERATIONS IN MEMORY DEVICES
Organization Name
Inventor(s)
Robert W. Mason of Boise ID (US)
Scott Anthony Stoller of Boise ID (US)
Pitamber Shukla of Boise ID (US)
Ekamdeep Singh of San Jose CA (US)
MANAGING DEFECTIVE BLOCKS DURING MULTI-PLANE PROGRAMMING OPERATIONS IN MEMORY DEVICES - A simplified explanation of the abstract
This abstract first appeared for US patent application 17897441 titled 'MANAGING DEFECTIVE BLOCKS DURING MULTI-PLANE PROGRAMMING OPERATIONS IN MEMORY DEVICES
Simplified Explanation
The abstract describes a system and method involving a memory device and a processing device. The processing device performs various operations on blocks within different planes of the memory device, including write operations, program verification checks, and failure verification operations.
- The processing device performs write operations on blocks in different planes of the memory device.
- If a block fails the program verification check, a counter value associated with another block is incremented.
- When the counter value meets a threshold criterion, a failure verification operation is performed on the second block.
- If the second block fails the failure verification operation, it is retired.
Potential Applications
- This technology can be used in memory devices to improve error detection and correction mechanisms.
- It can be applied in solid-state drives, embedded systems, and other memory-intensive applications.
Problems Solved
- Enhances the reliability and performance of memory devices by detecting and handling failures in individual blocks.
- Helps in maintaining data integrity and preventing data loss in memory systems.
Benefits
- Increases the overall reliability and lifespan of memory devices.
- Improves the efficiency of error detection and correction processes.
- Enhances the user experience by ensuring data integrity and minimizing the risk of data corruption.
Original Abstract Submitted
Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising performing a set of write operations on a first block in a first plane of the memory device and on a second block in a second plane of the memory device, performing a program verification check on the first block, responsive to determining that the first block fails the program verification check, incrementing a counter value associated with the second block; responsive to the counter value satisfying a threshold criterion, performing a failure verification operation on the second block, and responsive to determining that the second block fails the failure verification operation, retiring the second block.
