17896775. Memory Circuitry And Method Used In Forming Memory Circuitry simplified abstract (Micron Technology, Inc.)

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Memory Circuitry And Method Used In Forming Memory Circuitry

Organization Name

Micron Technology, Inc.

Inventor(s)

Jiewei Chen of Meridian ID (US)

Jordan D. Greenlee of Boise ID (US)

Shuangqiang Luo of Boise ID (US)

Silvia Borsari of Boise ID (US)

Memory Circuitry And Method Used In Forming Memory Circuitry - A simplified explanation of the abstract

This abstract first appeared for US patent application 17896775 titled 'Memory Circuitry And Method Used In Forming Memory Circuitry

Simplified Explanation

The memory circuitry described in the patent application comprises a unique structure involving vertically-alternating insulative tiers and conductive tiers, with channel-material strings of memory cells extending through these tiers in a memory-array region.

  • The memory circuitry includes a stack with insulative and conductive tiers arranged in a vertical alternating pattern.
  • Channel-material strings of memory cells run through the insulative and conductive tiers in a memory-array region.
  • The insulative and conductive tiers extend into a stair-step region, which includes a cavity with insulative material on top of conducting material forming a flight of stairs.
  • Conductive vias extend through the insulative material, with linings covering the sidewalls of the vias.
  • The conductive vias are positioned directly above and against the conducting material of the stairs.
    • Potential Applications:**
  • This technology could be applied in the development of high-density memory circuits for various electronic devices.
  • It may find use in data storage systems, computer memory modules, and other memory-intensive applications.
    • Problems Solved:**
  • The design of this memory circuitry allows for efficient vertical integration of memory cells, maximizing storage capacity in a compact space.
  • The unique structure helps in reducing signal interference and improving overall performance of the memory circuitry.
    • Benefits:**
  • Increased memory storage capacity within a smaller footprint.
  • Enhanced performance and reliability of memory circuits.
  • Potential for cost savings in memory module production due to efficient design.


Original Abstract Submitted

Memory circuitry comprising strings of memory cells comprises a stack comprising vertically-alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers in a memory-array region. The insulative tiers and the conductive tiers extend from the memory-array region into a stair-step region. The stair-step region comprises a cavity comprising a flight of stairs having insulative material atop treads of the stairs. Individual of the treads comprise conducting material of one of the conductive tiers. Conductive vias extend through the insulative material. Individual of the conductive vias are directly above and directly against the conducting material of the respective individual tread. A lining is over sidewalls of the individual conductive vias. The lining has a bottom. The individual conductive vias are directly under the bottom of the lining directly above the conducting material of the respective individual tread. Other embodiments, including method, are disclosed.

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