17895826. SYSTEMS AND TECHNIQUES FOR TIMING MISMATCH REDUCTION simplified abstract (Micron Technology, Inc.)

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SYSTEMS AND TECHNIQUES FOR TIMING MISMATCH REDUCTION

Organization Name

Micron Technology, Inc.

Inventor(s)

Yoshihito Morishita of Shibuya-ku (JP)

SYSTEMS AND TECHNIQUES FOR TIMING MISMATCH REDUCTION - A simplified explanation of the abstract

This abstract first appeared for US patent application 17895826 titled 'SYSTEMS AND TECHNIQUES FOR TIMING MISMATCH REDUCTION

Simplified Explanation

The patent application describes a device that includes a clock adjustment circuit to offset conditions affecting propagation delay of a clock signal in a memory device. The device comprises a differential amplifier, an inverter coupled to a first output of the differential amplifier, and a swing oscillator driver coupled to a second output of the inverter and an input of the differential amplifier. The swing oscillator driver includes a series of transistors, a signal path coupled to at least a first transistor of the series of transistors, and a strength control circuit coupled to the signal path to adjust the voltage of the signal.

  • The device includes a clock adjustment circuit with a differential amplifier, inverter, and swing oscillator driver.
  • The swing oscillator driver consists of a series of transistors and a signal path that transmits a signal with a specific voltage.
  • A strength control circuit is included to adjust the voltage of the signal transmitted by the signal path.

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      1. Potential Applications
  • Memory devices
  • Integrated circuits
  • Electronic devices requiring precise clock signals
      1. Problems Solved
  • Offset conditions affecting propagation delay of a clock signal
  • Ensuring accurate timing in memory devices
      1. Benefits
  • Improved performance of memory devices
  • Enhanced reliability of integrated circuits
  • Precise clock signal synchronization


Original Abstract Submitted

Systems and techniques to offset conditions affecting propagation delay of a clock signal in a memory device. These include a device that includes a clock adjustment circuit, comprising a differential amplifier, an inverter coupled to a first output of the differential amplifier, and a swing oscillator driver coupled to a second output of the inverter and an input of the differential amplifier. The swing oscillator driver includes a series of transistors, a signal path coupled to at least a first transistor of the series of transistors, wherein the signal path when in operation transmits a signal having a first voltage, and a strength control circuit coupled to the signal path, wherein the strength control circuit when in operation adjusts the first voltage of the signal to a second voltage.

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