17895017. FABRICATION METHOD OF A LATERAL 3D MEMORY DEVICE simplified abstract (Micron Technology, Inc.)
FABRICATION METHOD OF A LATERAL 3D MEMORY DEVICE
Organization Name
Inventor(s)
Yoshitaka Nakamura of Boise ID (US)
Scott E. Sills of Boise ID (US)
David K. Hwang of Boise ID (US)
FABRICATION METHOD OF A LATERAL 3D MEMORY DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 17895017 titled 'FABRICATION METHOD OF A LATERAL 3D MEMORY DEVICE
Simplified Explanation
The abstract describes methods and devices for a lateral three-dimensional memory device, including processes for forming thin film transistors, capacitor structures, and CMOS structures with specific temperature ranges.
- Thin film transistor is formed with a first thermal process at a certain temperature range.
- Capacitor bottom electrode is formed with a second thermal process at a lower temperature range than the thin film transistor.
- CMOS structure is formed with a third thermal process at a lower temperature range than the capacitor bottom electrode.
- Other parts of the capacitor structure are also formed.
Potential Applications
- Memory devices
- Integrated circuits
- Electronic devices
Problems Solved
- Efficient manufacturing of memory devices
- Improved thermal management during fabrication
- Enhanced performance and reliability of memory devices
Benefits
- Higher integration density
- Lower power consumption
- Improved device performance
- Enhanced reliability of memory devices
Original Abstract Submitted
Methods and devices for a lateral three-dimensional memory device, are described herein. One method includes forming a thin film transistor including a first thermal process having a first range of temperatures, forming a capacitor bottom electrode of a capacitor structure including a second thermal process having a second range of temperature, wherein a maximum temperature in the second range of temperatures is less than a maximum temperature in the first range of temperatures, forming a CMOS structure including a third thermal process having a third range of temperatures, wherein a maximum temperature in the third range of temperatures is less than a maximum temperature in the second range of temperatures, and forming at least one other part of the capacitor structure.
