17893681. STRUCTURES FOR WORD LINE MULTIPLEXING IN THREE-DIMENSIONAL MEMORY ARRAYS simplified abstract (Micron Technology, Inc.)
Contents
STRUCTURES FOR WORD LINE MULTIPLEXING IN THREE-DIMENSIONAL MEMORY ARRAYS
Organization Name
Inventor(s)
Fatma Arzum Simsek-ege of Boise ID (US)
Mingdong Cui of Folsom CA (US)
Richard E. Facekenthal of Carmichael CA (US)
STRUCTURES FOR WORD LINE MULTIPLEXING IN THREE-DIMENSIONAL MEMORY ARRAYS - A simplified explanation of the abstract
This abstract first appeared for US patent application 17893681 titled 'STRUCTURES FOR WORD LINE MULTIPLEXING IN THREE-DIMENSIONAL MEMORY ARRAYS
Simplified Explanation
- Explanation:**
- Methods, systems, and devices for word line multiplexing in three-dimensional memory arrays are described. - Memory die includes circuitry for access line multiplexing in regions adjacent to or between staircase regions. - Multiplexing region includes semiconductor material portions and gate material portions to modulate conductivity between them. - Word lines are coupled with semiconductor material portions and gate material portions to enable multiplexing techniques.
- Potential Applications:**
- Three-dimensional memory arrays - Semiconductor memory devices - Data storage systems
- Problems Solved:**
- Efficient word line multiplexing in memory arrays - Improved access line multiplexing in memory devices - Enhanced data storage capabilities
- Benefits:**
- Increased memory density - Faster data access speeds - Enhanced overall performance of memory arrays
Original Abstract Submitted
Methods, systems, and devices for structures for word line multiplexing in three-dimensional memory arrays are described. A memory die may include circuitry for access line multiplexing in regions adjacent to or between staircase regions. For example, a multiplexing region may include, for each word line of a stack of word lines, a respective first portion of a semiconductor material and a respective second portion of the semiconductor material, and may also include one or more gate material portions operable to modulate a conductivity between respective first and second portions. Each word line may be coupled with the respective first portion of the semiconductor material, such that biasing of the gate material portions may couple the word lines with the respective second portion of the semiconductor material. Such features may support various techniques for multiplexing associated with the stack of word lines, or among multiple stacks of word lines, or both.
