17893436. Memory Circuitry And Method Used In Forming Memory Circuitry simplified abstract (Micron Technology, Inc.)

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Memory Circuitry And Method Used In Forming Memory Circuitry

Organization Name

Micron Technology, Inc.

Inventor(s)

Matthew J. King of Boise ID (US)

Albert Fayrushin of Boise ID (US)

Sidhartha Gupta of Boise ID (US)

Jun Fujiki of Tokyo (JP)

Masashi Yoshida of Kanagawa (JP)

Yiping Wang of Boise ID (US)

Taehyun Kim of Boise ID (US)

Arun Kumar Dhayalan of Boise ID (US)

Memory Circuitry And Method Used In Forming Memory Circuitry - A simplified explanation of the abstract

This abstract first appeared for US patent application 17893436 titled 'Memory Circuitry And Method Used In Forming Memory Circuitry

Simplified Explanation

The abstract describes a method for forming a memory array with vertically-alternating tiers of memory cells, conductive masses, and channel-material strings.

  • Memory array formed by stacking different-composition tiers with channel-material strings.
  • Conductive masses made of conductively-doped semiconductive or metal material are electrically coupled to channel-material strings.
  • Upper channel-material strings of select-gate transistors are directly above and electrically coupled to the conductive masses.

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      1. Potential Applications
  • Memory storage devices
  • Solid-state drives
  • Computer memory modules
      1. Problems Solved
  • Increasing memory storage capacity
  • Improving memory array performance
  • Enhancing data retention and retrieval speed
      1. Benefits
  • Higher memory density
  • Faster data access
  • Improved overall performance of memory arrays


Original Abstract Submitted

A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating different-composition first tiers and second tiers. The stack comprises lower channel-material strings extending through the first tiers and the second tiers. Conductive masses are formed that comprise at least one of conductively-doped semiconductive material or conductive metal material. Individual of the conductive masses are atop and directly electrically coupled to individual of the lower channel-material strings. Upper channel-material strings of select-gate transistors are formed directly above the stack. Individual of the upper channel-material strings are directly above and directly electrically coupled to individual of the conductive masses. Other embodiments, including structure, are disclosed.