17888324. SPACER FOR CHIPS ON WAFER SEMICONDUCTOR DEVICE ASSEMBLIES simplified abstract (Micron Technology, Inc.)

SPACER FOR CHIPS ON WAFER SEMICONDUCTOR DEVICE ASSEMBLIES

Organization Name

Micron Technology, Inc.

Inventor(s)

Brandon P. Wirz of Boise ID (US)

Andrew M. Bayless of Boise ID (US)

Owen R. Fay of Meridian ID (US)

SPACER FOR CHIPS ON WAFER SEMICONDUCTOR DEVICE ASSEMBLIES - A simplified explanation of the abstract

This abstract first appeared for US patent application 17888324 titled 'SPACER FOR CHIPS ON WAFER SEMICONDUCTOR DEVICE ASSEMBLIES

Simplified Explanation

The patent application describes a semiconductor device assembly with a lower semiconductor die, a stack of upper semiconductor dies, a conductive package perimeter material surrounding the stack of upper semiconductor dies, and an encapsulant material between the sidewalls of the upper semiconductor dies and the conductive package perimeter material.

• Lower semiconductor die
• Stack of upper semiconductor dies
• Conductive package perimeter material
• Encapsulant material
• Method of forming semiconductor assemblies by stacking semiconductor die stacks, using pre-formed spacer assembly structures, disposing encapsulant material, and singulating the device wafer.

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1. 1. 1. Potential Applications

• Semiconductor manufacturing
• Electronics industry
• Integrated circuits

1. 1. 1. Problems Solved

• Ensuring proper alignment and spacing of semiconductor dies
• Protecting semiconductor dies from external elements
• Facilitating singulation process

1. 1. 1. Benefits

• Improved reliability of semiconductor devices
• Enhanced performance of electronic systems
• Streamlined manufacturing process

Original Abstract Submitted

A semiconductor device assembly, including a lower semiconductor die; a stack of upper semiconductor dies disposed over the lower semiconductor die; a conductive package perimeter material surrounding the stack of upper semiconductor dies; and an encapsulant material disposed between sidewalls of the stack of upper semiconductor dies and the conductive package perimeter material, and horizontally extending between the conductive package perimeter material and the lower semiconductor die. A method of forming a plurality of semiconductor assemblies, including stacking a plurality of semiconductor die stacks on a device wafer; disposing a pre-formed spacer assembly structure including a spacer material and a conductive package perimeter material around each of the plurality of semiconductor die stacks; disposing an encapsulant material between the conductive package perimeter material of the pre-formed spacer assembly structure and the corresponding semiconductor die stack; and singulating the device wafer to form the plurality of semiconductor device assemblies.