17884432. MULTI-LAYER CODE RATE ARCHITECTURE FOR SPECIAL EVENT PROTECTION WITH REDUCED PERFORMANCE PENALTY simplified abstract (Micron Technology, Inc.)
Contents
MULTI-LAYER CODE RATE ARCHITECTURE FOR SPECIAL EVENT PROTECTION WITH REDUCED PERFORMANCE PENALTY
Organization Name
Inventor(s)
Kishore Kumar Muchherla of Fremont CA (US)
Huai-Yuan Tseng of San Ramon CA (US)
Mustafa N. Kaynak of San Diego CA (US)
Sivagnanam Parthasarathy of Carlsbad CA (US)
Jonathan Scott Parry of Boise ID (US)
MULTI-LAYER CODE RATE ARCHITECTURE FOR SPECIAL EVENT PROTECTION WITH REDUCED PERFORMANCE PENALTY - A simplified explanation of the abstract
This abstract first appeared for US patent application 17884432 titled 'MULTI-LAYER CODE RATE ARCHITECTURE FOR SPECIAL EVENT PROTECTION WITH REDUCED PERFORMANCE PENALTY
Simplified Explanation
The patent application describes a system for providing multi-layer code rates for special event protection with reduced performance penalty for memories.
- Extra error correction code data is used to encode user data obtained from a host in anticipation of a stress event.
- User data and first error correction code data are written to a first block, while the extra error correction code data is written to a second block.
- After the stress event, pages with user data and extra error correction code data are scanned.
- If pages in the first block do not meet reliability requirements, a touch-up process is performed on each page to restore the block without needing the extra error correction code data.
- The extra error correction code data is removed from the second block, which can then be used for user data.
- Potential Applications
- Data storage systems - Memory devices - Special event protection systems
- Problems Solved
- Providing multi-layer code rates for special event protection - Reducing performance penalty for memories during stress events
- Benefits
- Enhanced data reliability during stress events - Efficient use of memory blocks - Improved error correction capabilities
Original Abstract Submitted
A system related to providing multi-layer code rates for special event protection with reduced performance penalty for memories is disclosed. Based on an impending stress event, extra error correction code data is utilized to encode user data obtained from a host. The user data and first error correction code data are written to a first block and the extra error correction code data is written to a second block. Upon stress event completion, pages having user data with the extra error correction code data are scanned. If pages of the first block are unable to satisfy reliability requirements, a touch-up process is executed on each page in the first block to reinstate the first block so that the extra error correction code data is no longer needed. The extra error correction code data is deleted from the second block and the second block is made available for user data.
