17883919. FINFETS WITH REDUCED PARASITICS simplified abstract (Micron Technology, Inc.)
Contents
FINFETS WITH REDUCED PARASITICS
Organization Name
Inventor(s)
FINFETS WITH REDUCED PARASITICS - A simplified explanation of the abstract
This abstract first appeared for US patent application 17883919 titled 'FINFETS WITH REDUCED PARASITICS
Simplified Explanation
The patent application describes an apparatus with a fin field-effect transistor that has a gate wrapping around fins to maintain good channel control and planar source and drain regions to reduce Miller capacitance and contact resistance.
- A fin field-effect transistor includes a bulk semiconductor region with planar source and drain regions structured as top portions of the bulk semiconductor region.
- One or more semiconductor fins contact the planar source and drain regions.
- The gate wraps around the semiconductor fins to control the channel effectively.
- Potential Applications
- Integrated circuits
- Microprocessors
- Memory devices
- Power amplifiers
- Problems Solved
- Reduced parasitic capacitance
- Lower contact resistance
- Improved channel control
- Benefits
- Higher performance
- Lower power consumption
- Enhanced reliability
Original Abstract Submitted
A variety of applications can include apparatus having a fin field-effect transistor with a gate wrapping around fins to maintain good channel control and planar source and drain regions to reduce Miller capacitance and contact resistance. The reduced parasitic capacitance and resistance can be translated into higher performance and lower power. A fin field-effect transistor can include a bulk semiconductor region having a planar source region structured as a first top portion of the bulk semiconductor region and a planar drain region structured as a second top portion of the bulk semiconductor region, with one or more semiconductor fins contacting the planar source region and the planar drain region with a gate wrapped around the one or more semiconductor fins.
