17878236. METAL GATE STACKS FOR CMOS SCALING simplified abstract (Micron Technology, Inc.)
Contents
METAL GATE STACKS FOR CMOS SCALING
Organization Name
Inventor(s)
Pengyuan Zheng of Boise ID (US)
Yongjun Jeff Hu of Boise ID (US)
METAL GATE STACKS FOR CMOS SCALING - A simplified explanation of the abstract
This abstract first appeared for US patent application 17878236 titled 'METAL GATE STACKS FOR CMOS SCALING
Simplified Explanation
The abstract of the patent application describes an apparatus that includes a memory device with an array of memory cells and a complementary metal-oxide-semiconductor (CMOS) device connected to the array. The CMOS device consists of a gate electrode that contacts the polysilicon gates of a p-channel metal-oxide-semiconductor (PMOS) transistor and an n-channel metal-oxide-semiconductor (NMOS) transistor. The gate electrode is a multi-metal stack, which can have two levels of different metal compositions.
- The patent application describes an apparatus with a memory device and a CMOS device.
- The CMOS device includes a gate electrode that contacts the PMOS and NMOS transistors.
- The gate electrode is a multi-metal stack with two levels of different metal compositions.
Potential applications of this technology:
- Memory devices in electronic devices such as smartphones, tablets, and computers.
- Integrated circuits and microprocessors.
- Data storage devices and systems.
Problems solved by this technology:
- Improved performance and efficiency of memory devices.
- Enhanced functionality and reliability of integrated circuits.
- Increased data storage capacity and speed.
Benefits of this technology:
- Faster data processing and retrieval.
- Lower power consumption and improved energy efficiency.
- Higher storage capacity and improved reliability.
Original Abstract Submitted
A variety of applications can include apparatus having a memory device structured with an array of memory cells and a complementary metal-oxide-semiconductor (CMOS) device coupled to the array. The CMOS device can include a gate electrode on and contacting the polysilicon gates of a p-channel metal-oxide-semiconductor (PMOS) transistor and a n-channel metal-oxide-semiconductor (NMOS) transistor of the CMOS device, where the gate electrode is a multi-metal stack. The multi-metal stack of the gate electrode can be two levels of different metal compositions.
