17877296. MEMORY WITH PARTIAL ARRAY DENSITY SECURITY, AND ASSOCIATED SYSTEMS, DEVICES, AND METHODS simplified abstract (Micron Technology, Inc.)

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MEMORY WITH PARTIAL ARRAY DENSITY SECURITY, AND ASSOCIATED SYSTEMS, DEVICES, AND METHODS

Organization Name

Micron Technology, Inc.

Inventor(s)

Michael A. Shore of Boise ID (US)

Nathaniel J. Meier of Boise ID (US)

MEMORY WITH PARTIAL ARRAY DENSITY SECURITY, AND ASSOCIATED SYSTEMS, DEVICES, AND METHODS - A simplified explanation of the abstract

This abstract first appeared for US patent application 17877296 titled 'MEMORY WITH PARTIAL ARRAY DENSITY SECURITY, AND ASSOCIATED SYSTEMS, DEVICES, AND METHODS

Simplified Explanation

The abstract describes a memory system with partial array density security. It includes a memory region with multiple rows, columns, and cells. The rows consist of both enabled and disabled memory rows, with sets of disabled rows interleaved with enabled rows. The apparatus can only access the enabled memory rows for reading or writing data. Additionally, the disabled memory rows are refreshed using a different protocol than the enabled memory rows.

  • The memory system has a memory region with multiple rows, columns, and cells.
  • Enabled and disabled memory rows are present in the memory region.
  • Sets of disabled memory rows are interleaved with enabled memory rows.
  • Only the enabled memory rows can be accessed for reading or writing data.
  • The disabled memory rows are refreshed using a different protocol than the enabled memory rows.

Potential applications of this technology:

  • Enhanced security in memory systems by selectively enabling and disabling memory rows.
  • Protection against unauthorized access or tampering of data stored in memory.
  • Improved data privacy and confidentiality in memory systems.

Problems solved by this technology:

  • Mitigates the risk of data breaches or unauthorized access to sensitive information stored in memory.
  • Provides an additional layer of security for memory systems.
  • Reduces the vulnerability of memory systems to attacks or data leaks.

Benefits of this technology:

  • Enhanced security and protection for data stored in memory.
  • Flexibility in enabling or disabling memory rows based on specific requirements.
  • Efficient use of memory resources by interleaving disabled memory rows with enabled rows.
  • Different refresh protocols for enabled and disabled memory rows optimize memory performance and reliability.


Original Abstract Submitted

Memory with partial array density security is disclosed herein. In one embodiment, an apparatus comprises a memory region including a plurality of memory rows, a plurality of memory columns, and a plurality of memory cells arranged at intersections of the plurality of memory rows and the plurality of memory columns. The plurality of memory rows includes a plurality of enabled memory rows and a plurality of disabled memory rows. Sets of one or more disabled memory rows are interleaved with enabled memory rows within the memory region. To write data to or read data from the memory region, the apparatus can be configured to access only the enabled memory rows of the memory region. The apparatus may further be configured to refresh disabled memory rows of the memory region according to a different refresh protocol from a refresh protocol used to refresh the enabled memory rows of the memory region.

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