17875778. SEMICONDUCTOR DEVICE ASSEMBLY INTERCONNECTION PILLARS AND ASSOCIATED METHODS simplified abstract (Micron Technology, Inc.)

SEMICONDUCTOR DEVICE ASSEMBLY INTERCONNECTION PILLARS AND ASSOCIATED METHODS

Organization Name

Micron Technology, Inc.

Inventor(s)

Andrew M. Bayless of Boise ID (US)

Cassie M. Bayless of Boise ID (US)

Brandon P. Wirz of Boise ID (US)

SEMICONDUCTOR DEVICE ASSEMBLY INTERCONNECTION PILLARS AND ASSOCIATED METHODS - A simplified explanation of the abstract

This abstract first appeared for US patent application 17875778 titled 'SEMICONDUCTOR DEVICE ASSEMBLY INTERCONNECTION PILLARS AND ASSOCIATED METHODS

Simplified Explanation

The abstract describes an interconnection structure that connects two semiconductor dies. The structure includes conductive pillars with bonding surfaces, barrier layers, and solder layers. The first portion of the structure surrounds the first conductive pillar, while the second portion surrounds the second conductive pillar. The bonding surfaces of the pillars are coupled together.

• The interconnection structure physically and electrically connects two semiconductor dies.
• It includes conductive pillars with concave and convex bonding surfaces.
• Barrier layers surround the sidewall of the first conductive pillar.
• Solder layers surround the barrier layers.
• The bonding surfaces of the pillars are coupled together.
• The structure allows for efficient and reliable interconnection between the semiconductor dies.

Potential Applications:

• Semiconductor packaging and assembly
• Integrated circuits
• Electronic devices

Problems Solved:

• Provides a reliable and efficient interconnection between semiconductor dies.
• Helps in improving the performance and functionality of electronic devices.
• Reduces the risk of electrical and physical damage during interconnection.

Benefits:

• Enhanced electrical and physical coupling between semiconductor dies.
• Improved reliability and performance of electronic devices.
• Cost-effective and efficient interconnection process.

Original Abstract Submitted

In some embodiments, an interconnection structure can electrically and physically couple a first semiconductor die and a second semiconductor die. The interconnection structure can include a first portion at the first semiconductor die and a second portion at the second semiconductor die. The first portion can include a first conductive pillar with a concave bonding surface, a first annular barrier layer, and a first annular solder layer. The first annular barrier layer can surround a sidewall of the first conductive pillar, and the first annular solder layer can surround the first barrier layer. The second portion can include a second conductive pillar having a convex bonding surface, the convex bonding surface coupled to the concave bonding surface. The second interconnection structure can further include a second annular solder layer surrounding a second annular barrier layer surrounding the second conductive pillar.