17848844. THREE-DIMENSIONAL STORAGE DEVICE USING WAFER-TO-WAFER BONDING simplified abstract (Samsung Electronics Co., Ltd.)

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THREE-DIMENSIONAL STORAGE DEVICE USING WAFER-TO-WAFER BONDING

Organization Name

Samsung Electronics Co., Ltd.

Inventor(s)

Eun Chu Oh of Hwaseong-si (KR)

Byungchul Jang of Suwon-si (KR)

Junyeong Seok of Seoul (KR)

Younggul Song of Hwaseong-si (KR)

Joonsung Lim of Seongnam-si (KR)

THREE-DIMENSIONAL STORAGE DEVICE USING WAFER-TO-WAFER BONDING - A simplified explanation of the abstract

This abstract first appeared for US patent application 17848844 titled 'THREE-DIMENSIONAL STORAGE DEVICE USING WAFER-TO-WAFER BONDING

Simplified Explanation

The abstract describes a three-dimensional storage device that uses wafer-to-wafer bonding. It consists of two chips: the first chip has a substrate and a peripheral circuit region with control logic, while the second chip has a substrate and three-dimensional arrays of non-volatile memory cells. The second chip is stacked on top of the first chip, with the control logic circuit on the opposite surface of the second substrate.

  • The storage device uses wafer-to-wafer bonding to stack two chips together.
  • The first chip contains a control logic circuit to control the operation modes of the non-volatile memory device.
  • The second chip contains three-dimensional arrays of non-volatile memory cells.
  • The second chip is stacked on top of the first chip, with the control logic circuit on the opposite surface of the second substrate.

Potential Applications

  • This technology can be used in various electronic devices that require high-density storage, such as smartphones, tablets, and laptops.
  • It can also be applied in data centers and servers to increase storage capacity and improve performance.

Problems Solved

  • The three-dimensional storage device solves the problem of limited storage capacity in electronic devices by stacking multiple memory chips together.
  • It also addresses the need for faster and more efficient storage solutions by integrating control logic circuits within the stacked chips.

Benefits

  • The wafer-to-wafer bonding technique allows for compact and efficient stacking of chips, enabling higher storage density.
  • The integration of control logic circuits within the stacked chips reduces the need for external control circuits, saving space and improving overall performance.
  • The three-dimensional storage device offers increased storage capacity and improved data access speeds, enhancing the user experience.


Original Abstract Submitted

Provided is a three-dimensional storage device using wafer-to-wafer bonding. A storage device includes a first chip including a first substrate and a peripheral circuit region including a first control logic circuit configured to control operation modes of the non-volatile memory device and a second chip including a second substrate and three-dimensional arrays of non-volatile memory cells. The second chip may be vertically stacked on the first chip so that a first surface of the first substrate faces a first surface of the second substrate, and a second control logic circuit is configured to control operation conditions of the non-volatile memory device and is arranged on a second surface of the second substrate, the second surface of the second substrate being opposite to the first surface of the second substrate of the second chip.

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