17836711. SEMICONDUCTOR PACKAGE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)

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SEMICONDUCTOR PACKAGE

Organization Name

SAMSUNG ELECTRONICS CO., LTD.

Inventor(s)

Jae-Ean Lee of Suwon-si (KR)

Gyu Jin Choi of Asan-si (KR)

SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract

This abstract first appeared for US patent application 17836711 titled 'SEMICONDUCTOR PACKAGE

Simplified Explanation

The semiconductor package described in this patent application includes a substrate, a semiconductor chip, an interposer, a conductive pad, and a connecting portion.

  • The substrate is the base on which the other components are mounted.
  • The first semiconductor chip is placed on the upper surface of the substrate.
  • The interposer is positioned on top of the first semiconductor chip.
  • The conductive pad is located on the upper surface of the substrate.
  • The connecting portion is situated between the upper surface of the substrate and the lower surface of the interposer.
  • The connecting portion electrically connects the conductive pad and the interposer.
  • The connecting portion is spaced apart from the first semiconductor chip along a horizontal direction parallel to the upper surface of the substrate.
  • The connecting portion consists of a first metal layer, a second metal layer, and a metal post.
  • The first metal layer is on the conductive pad.
  • The second metal layer is on the first metal layer.
  • The metal post is on the second metal layer.
  • The first metal layer, second metal layer, and metal post are made of different metals.

Potential applications of this technology:

  • Semiconductor packaging for electronic devices
  • Integrated circuits
  • Microprocessors

Problems solved by this technology:

  • Provides a reliable and efficient electrical connection between the conductive pad and the interposer
  • Allows for proper functioning and communication between the semiconductor chip and other components
  • Reduces the risk of electrical failures or malfunctions

Benefits of this technology:

  • Improved performance and reliability of semiconductor packages
  • Enhanced electrical connectivity and signal transmission
  • Enables the development of smaller and more compact electronic devices.


Original Abstract Submitted

A semiconductor package is provided. The semiconductor package includes: a substrate; a first semiconductor chip provided on an upper surface of the substrate; an interposer provided on the first semiconductor chip; a conductive pad provided on the upper surface of the substrate; and a connecting portion provided between the upper surface of the substrate and a lower surface of the interposer, wherein the connecting portion is spaced apart from the first semiconductor chip along a horizontal direction parallel to the upper surface of the substrate, and electrically connects the conductive pad and the interposer, and the connecting portion includes a first metal layer provided on the conductive pad, a second metal layer provided on the first metal layer, and a metal post provided on the second metal layer, wherein the first metal layer includes a first metal, the second metal layer includes a second metal different from the first metal, and the metal post includes a third metal different from the first metal and the second metal.