17823443. Asymmetric Read-Write Sequence for Interconnected Dies simplified abstract (Micron Technology, Inc.)
Asymmetric Read-Write Sequence for Interconnected Dies
Organization Name
Inventor(s)
Kang-Yong Kim of Boise ID (US)
Jason Mcbride Brown of Austin TX (US)
Venkatraghavan Bringivijayaraghavan of Hyderabad (IN)
Vijayakrishna J. Vankayala of Allen TX (US)
Asymmetric Read-Write Sequence for Interconnected Dies - A simplified explanation of the abstract
This abstract first appeared for US patent application 17823443 titled 'Asymmetric Read-Write Sequence for Interconnected Dies
Simplified Explanation
The patent application describes apparatuses and techniques for implementing an asymmetric read-write sequence for interconnected dies.
- An asymmetric die-access sequence for read versus write operations is established.
- Data is written to or read from interface and linked dies in a specific order.
- The read and write operations can be chosen to account for delays in transferring data between the interconnected dies.
- Asymmetric read-write burst sequences help minimize the impact of timing delays on memory device operations.
Potential Applications
- Memory devices
- Interconnected die architectures
- Data transfer systems
Problems Solved
- Minimizing timing delays in data transfer between interconnected dies
- Improving overall timing of read and write operations in memory devices
Benefits
- Enhanced efficiency in data transfer processes
- Improved performance of memory devices
- Reduced impact of timing delays on memory operations
Original Abstract Submitted
Apparatuses and techniques for implementing an asymmetric read-write sequence for interconnected dies are described. The asymmetric read-write sequence refers to an asymmetric die-access sequence for read versus write operations. The “asymmetric” term refers to a difference in an order in which data is written to or read from interface and linked dies of the interconnected die architecture. The orders for the read and write operations can be chosen such that a delay associated with transferring data between the interconnected dies occurs as data passes between the interface die and a memory controller. With asymmetric read-write burst sequences, overall timing of the read and write operations of a memory device may be impacted less, if at all, by a timing delay associated with the interconnected die architecture.
