17823349. MULTI-CHIP PACKAGE WITH ENHANCED CONDUCTIVE LAYER ADHESION simplified abstract (Micron Technology, Inc.)
MULTI-CHIP PACKAGE WITH ENHANCED CONDUCTIVE LAYER ADHESION
Organization Name
Inventor(s)
Kelvin Aik Boo Tan of Singapore (SG)
Chin Hui Chong of Singapore (SG)
MULTI-CHIP PACKAGE WITH ENHANCED CONDUCTIVE LAYER ADHESION - A simplified explanation of the abstract
This abstract first appeared for US patent application 17823349 titled 'MULTI-CHIP PACKAGE WITH ENHANCED CONDUCTIVE LAYER ADHESION
Simplified Explanation
The patent application describes methods, systems, and devices for a multi-chip package with enhanced conductive layer adhesion.
- A conductive layer, such as a conductive trace, is formed above a substrate.
- An integrated circuit is bonded to the conductive layer.
- An encapsulant is deposited between the integrated circuit and the conductive layer.
- Surface features or recesses are formed on or within the conductive layer to which the encapsulant adheres.
Potential Applications
- Semiconductor packaging
- Electronics manufacturing
- Integrated circuit assembly
Problems Solved
- Improved adhesion between the conductive layer and the encapsulant
- Enhanced reliability of the multi-chip package
- Better protection for the integrated circuit
Benefits
- Increased durability of the package
- Enhanced performance of the integrated circuit
- Improved overall quality of the electronic device
Original Abstract Submitted
Methods, systems, and devices for multi-chip package with enhanced conductive layer adhesion are described. In some examples, a conductive layer (e.g., a conductive trace) may be formed above a substrate. An integrated circuit may be bonded to the conductive layer and an encapsulant may be deposited at least between the integrated circuit and the conductive layer. In some examples, one or more surface features or one or more recesses may be formed on or within the conductive layer and the encapsulant may adhere to the surface features or recesses.
