17822032. SYSTEMS AND METHODS FOR TESTING REDUNDANT FUSE LATCHES IN A MEMORY DEVICE simplified abstract (Micron Technology, Inc.)

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SYSTEMS AND METHODS FOR TESTING REDUNDANT FUSE LATCHES IN A MEMORY DEVICE

Organization Name

Micron Technology, Inc.

Inventor(s)

Yoshinori Fujiwara of Boise ID (US)

Takuya Tamano of Boise ID (US)

Jason M. Johnson of Nampa ID (US)

Kevin G. Werhane of Kuna ID (US)

Daniel S. Miller of Boise ID (US)

SYSTEMS AND METHODS FOR TESTING REDUNDANT FUSE LATCHES IN A MEMORY DEVICE - A simplified explanation of the abstract

This abstract first appeared for US patent application 17822032 titled 'SYSTEMS AND METHODS FOR TESTING REDUNDANT FUSE LATCHES IN A MEMORY DEVICE

Simplified Explanation

The abstract describes an electronic device with multiple memory elements, including redundant memory elements, and repair circuitry to remap data when a failure occurs.

  • The electronic device has multiple memory elements, including redundant ones.
  • Repair circuitry is included to remap data when a failure happens.
  • The repair circuitry consists of multiple fuse latches for implementing the remapping.
  • Latch testing circuitry is also part of the repair circuitry to test the functionality of the fuse latches.
  • Selection circuitry enables the testing of a first set of fuse latches separately from the unselected second set.
      1. Potential Applications
  • Data storage devices
  • Embedded systems
  • Automotive electronics
      1. Problems Solved
  • Data loss due to memory element failures
  • Improving reliability and durability of electronic devices
      1. Benefits
  • Enhanced data integrity
  • Increased device longevity
  • Improved overall performance and reliability


Original Abstract Submitted

An electronic device includes multiple memory elements including multiple redundant memory elements. The electronic device also includes repair circuitry configured to remap data to the multiple memory elements when a failure occurs. The repair circuitry includes multiple fuse latches configured to implement the remapping. The repair circuitry also includes latch testing circuitry configured to test functionality of the multiple fuse latches. The latch testing circuitry includes selection circuitry configured to enable selection of a first set of fuse latches of the multiple fuse latches for a test separate from a second set of fuse latches of the multiple fuse latches that are unselected by the selection circuitry.

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