17821740. Synchronous Input Buffer Control Using a State Machine simplified abstract (Micron Technology, Inc.)

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Synchronous Input Buffer Control Using a State Machine

Organization Name

Micron Technology, Inc.

Inventor(s)

Kallol Mazumder of Dallas TX (US)

Navya Sri Sreeram of Plano TX (US)

Synchronous Input Buffer Control Using a State Machine - A simplified explanation of the abstract

This abstract first appeared for US patent application 17821740 titled 'Synchronous Input Buffer Control Using a State Machine

Simplified Explanation

The memory device described in the patent application includes a command interface, an input buffer, and a state machine.

  • The command interface receives write commands from a host device.
  • The input buffer buffers data from the host device.
  • The state machine receives a command into a first partition and enables a data strobe (DQS) input buffer in response.
  • The state machine maintains the enablement of the DQS input buffer while the command traverses the state machine.
  • The state machine disables the DQS input buffer after a set duration of time.

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      1. Potential Applications
  • Memory devices in electronic devices such as smartphones, tablets, and computers.
  • Data storage devices in servers and data centers.
      1. Problems Solved
  • Efficient handling of write commands from a host device.
  • Proper buffering of data to ensure smooth operation of the memory device.
      1. Benefits
  • Improved performance and reliability of memory devices.
  • Enhanced data transfer speeds.
  • Better overall user experience with electronic devices.


Original Abstract Submitted

A memory device includes a command interface configured to receive write commands from a host device. The memory device also includes an input buffer configured to buffer data from the host device. Additionally, the memory device includes a state machine configured to receive a command into a first partition of the state machine and to enable a data strobe (DQS) input buffer in response to the indication. The state machine is also configured to maintain the enablement of the DQS input buffer while the command traverses the state machine. Furthermore, the state machine is configured to disable the DQS input buffer after a set duration of time.

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