17821676. MEMORY WITH PARALLEL MAIN AND TEST INTERFACES simplified abstract (Micron Technology, Inc.)
Contents
MEMORY WITH PARALLEL MAIN AND TEST INTERFACES
Organization Name
Inventor(s)
James Brian Johnson of Boise ID (US)
Kunal R. Parekh of Boise ID (US)
Eiichi Nakano of Boise ID (US)
Amy Rae Griffin of Boise ID (US)
MEMORY WITH PARALLEL MAIN AND TEST INTERFACES - A simplified explanation of the abstract
This abstract first appeared for US patent application 17821676 titled 'MEMORY WITH PARALLEL MAIN AND TEST INTERFACES
Simplified Explanation
The patent application describes methods, systems, and devices for memory with parallel main and test interfaces. A memory die is configured with parallel interfaces that can individually support evaluation operations or access operations.
- Memory die has parallel interfaces for evaluation and access operations
- First set of contacts for communicating signaling with other memory dies in a stack
- Second set of contacts for probing for pre-assembly evaluations, electrically isolated from the first set
- Evaluation operations can be performed using the second set of contacts without damaging the first set
Potential applications of this technology:
- Memory devices in multiple-die stacks
- Testing and evaluation of memory dies before and after assembly in a stack
Problems solved by this technology:
- Damage to contacts during evaluation operations
- Improved capabilities for supporting multiple-die stacks in memory devices
Benefits of this technology:
- Enhanced testing and evaluation processes for memory dies
- Increased reliability and efficiency in memory devices with multiple-die stacks
Original Abstract Submitted
Methods, systems, and devices for memory with parallel main and test interfaces are described. A memory die may be configured with parallel interfaces that may individually (e.g., separately) support evaluation operations (e.g., before or as part of assembly in a multiple-die stack) or access operations (e.g., after assembly in a multiple die stack). For example, a memory die may include a first set of one or more contacts that support communicating signaling with or via another memory die in a multiple-die stack. The memory die may also include a second set of one or more contacts that support probing for pre-assembly evaluations, which may be electrically isolated from the first set of contacts. By implementing such parallel interfaces, evaluation operations may be performed using the second set of contacts without damaging the first set of contacts, which may improve capabilities for supporting a multiple-die stack in a memory device.
