17819569. PILLAR AND WORD LINE PLATE ARCHITECTURE FOR A MEMORY ARRAY simplified abstract (Micron Technology, Inc.)

PILLAR AND WORD LINE PLATE ARCHITECTURE FOR A MEMORY ARRAY

Organization Name

Micron Technology, Inc.

Inventor(s)

Lorenzo Fratin of Buccinasco (IT)

Enrico Varesi of Milano (IT)

Paolo Fantini of Vimercate (IT)

Thomas M. Graettinger of Boise ID (US)

PILLAR AND WORD LINE PLATE ARCHITECTURE FOR A MEMORY ARRAY - A simplified explanation of the abstract

This abstract first appeared for US patent application 17819569 titled 'PILLAR AND WORD LINE PLATE ARCHITECTURE FOR A MEMORY ARRAY

Simplified Explanation

The patent application describes methods, systems, and devices for pillar and word line plate architecture in a memory array.

• Memory array includes word line plate at each vertical level, coupled with memory cells of a word line tile.
• Multiple pillars in the array, each with two or more electrodes separated by insulating dielectric material.
• Each electrode of the pillar is coupled with a set of memory cells at different levels in the array.
• Electrode and word line plate are addressed to access a specific memory cell.

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1. 1. 1. Potential Applications

• High-density memory arrays in electronic devices
• Data storage in computers, smartphones, and other devices

1. 1. 1. Problems Solved

• Efficient organization of memory cells in a vertical structure
• Improved access to specific memory cells in the array

1. 1. 1. Benefits

• Increased memory storage capacity
• Faster access to data
• Enhanced performance in electronic devices

Original Abstract Submitted

Methods, systems, and devices for pillar and word line plate architecture for a memory array are described to support a memory array that may include a word line plate at each vertical level of the memory array, where the word line plate may be coupled with each memory cell of a word line tile at the respective level. The memory array includes multiple pillars, where each pillar includes two or more electrodes that run the vertical length of the pillar and which are separated by an insulating dielectric material. Each electrode of the pillar is coupled with a corresponding set of memory cells, with each memory cell located at a different level of the array. An electrode of the pillar mis addressed, along with a word line plate of the memory array, to access a memory cell associated with the electrode and word line plate.