17743819. 3D LAMINATED CHIP, AND SEMICONDUCTOR PACKAGE INCLUDING THE 3D LAMINATED CHIP simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)

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3D LAMINATED CHIP, AND SEMICONDUCTOR PACKAGE INCLUDING THE 3D LAMINATED CHIP

Organization Name

SAMSUNG ELECTRONICS CO., LTD.

Inventor(s)

Eunseok Song of Hwaseong-si (KR)

3D LAMINATED CHIP, AND SEMICONDUCTOR PACKAGE INCLUDING THE 3D LAMINATED CHIP - A simplified explanation of the abstract

This abstract first appeared for US patent application 17743819 titled '3D LAMINATED CHIP, AND SEMICONDUCTOR PACKAGE INCLUDING THE 3D LAMINATED CHIP

Simplified Explanation

The abstract describes a patent application for a 3D laminated chip that consists of three semiconductor chips arranged in a horizontal stack. The first chip has a through electrode, and the second chip is placed next to it. The third chip is larger in size than the first chip and is positioned on top of both the first and second chips.

  • The patent application is for a 3D laminated chip with multiple semiconductor chips stacked together.
  • The first chip contains a through electrode, which allows for electrical connections to be made through the chip.
  • The second chip is placed horizontally adjacent to the first chip.
  • The third chip, which is larger in size than the first chip, is positioned on top of both the first and second chips.

Potential Applications:

  • This technology could be used in various electronic devices such as smartphones, tablets, and computers.
  • It can be applied in the automotive industry for advanced driver assistance systems (ADAS) and autonomous vehicles.
  • The 3D laminated chip can be utilized in medical devices, aerospace systems, and industrial automation.

Problems Solved:

  • The 3D laminated chip allows for a more compact and efficient design by stacking multiple chips together.
  • It enables improved performance and functionality in electronic devices by integrating multiple semiconductor chips.
  • The through electrode in the first chip facilitates efficient electrical connections within the stack.

Benefits:

  • The compact design of the 3D laminated chip saves space and allows for smaller and thinner electronic devices.
  • The integration of multiple chips enhances the performance and capabilities of electronic devices.
  • The through electrode enables efficient electrical connections, improving the overall functionality of the chip.


Original Abstract Submitted

A three-dimensional (3D) laminated chip that includes a first semiconductor chip including a first through electrode disposed therein. A second semiconductor chip is arranged horizontally adjacent to the first semiconductor chip. A third semiconductor chip is arranged on the first semiconductor chip and the second semiconductor chip. A size of the third semiconductor chip is greater than a size of the first semiconductor chip.

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