SEARCH RESULTS for assignor:"CHEN, KUEI-SHUN"

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(X0) 14706871: EXPOSURE METHOD OF WAFER SUBSTRATE, MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, AND EXPOSURE TOOL

(A1) 20160124323: EXPOSURE METHOD OF WAFER SUBSTRATE, MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, AND EXPOSURE TOOL

(B2) 1: EXPOSURE METHOD OF WAFER SUBSTRATE, MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, AND EXPOSURE TOOL

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Patent(s)

(X0) 14706871: EXPOSURE METHOD OF WAFER SUBSTRATE, MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, AND EXPOSURE TOOL

(A1) 20160124323: EXPOSURE METHOD OF WAFER SUBSTRATE, MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, AND EXPOSURE TOOL

(B2) 1: EXPOSURE METHOD OF WAFER SUBSTRATE, MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, AND EXPOSURE TOOL

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(X0) 15395310: Directional Patterning Methods

(A1) 20180090370: Directional Patterning Methods

(B2) 1: Directional Patterning Methods

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(X0) 15945356: Method and Structure for Mandrel and Spacer Patterning

(A1) 20180225404: Method and Structure for Mandrel and Spacer Patterning

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(X0) 15474522: Pattern Fidelity Enhancement with Directional Patterning Technology

(A1) 20180174853: Pattern Fidelity Enhancement with Directional Patterning Technology

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(X0) 15474522: Pattern Fidelity Enhancement with Directional Patterning Technology

(A1) 20180174853: Pattern Fidelity Enhancement with Directional Patterning Technology

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(X0) 15352118: FORMATION METHOD OF SEMICONDUCTOR DEVICE STRUCTURE USING PATTERNING STACKS

(A1) 20180138034: FORMATION METHOD OF SEMICONDUCTOR DEVICE STRUCTURE USING PATTERNING STACKS

(B2) 9: FORMATION METHOD OF SEMICONDUCTOR DEVICE STRUCTURE USING PATTERNING STACKS

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(X0) 14801383: Method and Structure for Mandrel and Spacer Patterning

(A1) 20170017745: Method and Structure for Mandrel and Spacer Patterning

(B2) 9: Method and Structure for Mandrel and Spacer Patterning

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(X0) 15250023: DUMMY GATE STRUCTURE AND METHODS THEREOF

(A1) 20160365428: DUMMY GATE STRUCTURE AND METHODS THEREOF

(B2) 9: DUMMY GATE STRUCTURE AND METHODS THEREOF

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(X0) 14841173: Method for Integrated Circuit Patterning

(A1) 20170062222: Method for Integrated Circuit Patterning

(B2) 9: Method for Integrated Circuit Patterning

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(X0) 15411613: Method for Improving Circuit Layout for Manufacturability

(A1) 20180096090: Method for Improving Circuit Layout for Manufacturability

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(X0) 15720593: SEMICONDUCTOR DEVICE HAVING NON-ORTHOGONAL ELEMENT

(A1) 20180025968: SEMICONDUCTOR DEVICE HAVING NON-ORTHOGONAL ELEMENT

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(X0) 15783448: Method and Structure for Gap Filling Improvement

(A1) 20180040617: Method and Structure for Gap Filling Improvement