VERTICAL PN CONNECTION IN MULTI-STACK SEMICONDUCTOR DEVICE: abstract simplified (17841299)

• This abstract for appeared for patent application number 17841299 Titled 'VERTICAL PN CONNECTION IN MULTI-STACK SEMICONDUCTOR DEVICE'

Simplified Explanation

The abstract describes a multi-stack semiconductor device that consists of a substrate and two field-effect transistors. The lower transistor has a lower channel structure, a lower gate structure, and two source/drain regions. The upper transistor is placed on top of the lower transistor and has an upper channel structure, an upper gate structure, and two source/drain regions positioned vertically above the source/drain regions of the lower transistor. The first source/drain region is connected to either a positive or negative voltage source, while the third source/drain region is connected to the opposite voltage source. Additionally, the top portion of the second source/drain region and the bottom portion of the fourth source/drain region are connected to each other.

Original Abstract Submitted

A multi-stack semiconductor device includes: a substrate; a lower field-effect transistor including a lower channel structure, a lower gate structure surrounding the lower channel structure, and 1and 2source/drain regions; and an upper field-effect transistor, on the lower field-effect transistor, including an upper channel structure, an upper gate structure surrounding the upper channel structure, and 3and 4source/drain regions vertically above the 1and 2source/drain regions, respectively, wherein the 1source/drain region is connected to one of a positive voltage source and a negative voltage source, and the 3source/drain region is connected to the other of the positive voltage source and the negative voltage source, and wherein a top portion of the 2source/drain region and a bottom portion the 4source/drain region are connected to each other.