US Patent Application 18332706. REFRESH ADDRESS GENERATION CIRCUIT AND METHOD, MEMORY, AND ELECTRONIC DEVICE simplified abstract

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REFRESH ADDRESS GENERATION CIRCUIT AND METHOD, MEMORY, AND ELECTRONIC DEVICE

Organization Name

CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor(s)

Yinchuan Gu of Hefei City (CN)

REFRESH ADDRESS GENERATION CIRCUIT AND METHOD, MEMORY, AND ELECTRONIC DEVICE - A simplified explanation of the abstract

This abstract first appeared for US patent application 18332706 titled 'REFRESH ADDRESS GENERATION CIRCUIT AND METHOD, MEMORY, AND ELECTRONIC DEVICE

Simplified Explanation

The patent application describes a refresh address generation circuit.

  • The circuit includes a refresh control circuit that receives refresh commands and performs refresh operations.
  • The refresh control circuit outputs a first clock signal when the number of refresh operations is below a preset value, and a second clock signal when the number of refresh operations is equal to the preset value.
  • An address generator is coupled to the refresh control circuit and stores a first address.
  • The address generator outputs a to-be-refreshed address in response to the first clock signal during each refresh operation.
  • The to-be-refreshed address includes the first address, and the first address is changed in response to the second clock signal.


Original Abstract Submitted

A refresh address generation circuit includes: a refresh control circuit configured to sequentially receive first refresh commands and perform first refresh operations respectively, output a first clock signal when the number of the first refresh operations is less than a preset value or output a second clock signal when the number of the first refresh operations is equal to the preset value n, where n is a positive integer greater than or equal to 1; an address generator coupled to refresh control circuit, pre-storing a first address, receiving the first clock signal or the second clock signal, outputting a first to-be-refreshed address in response to the first clock signal during each first refresh operation, the first to-be-refreshed address includes the first address, and changing the first address in response to the second clock signal.

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