US Patent Application 18169159. TIMING SEQUENCE CONTROL CIRCUIT, TIMING SEQUENCE CONTROL METHOD, AND SEMICONDUCTOR MEMORY simplified abstract
Contents
TIMING SEQUENCE CONTROL CIRCUIT, TIMING SEQUENCE CONTROL METHOD, AND SEMICONDUCTOR MEMORY
Organization Name
CHANGXIN MEMORY TECHNOLOGIES, INC.
Inventor(s)
Kangling Ji of Hefei City (CN)
TIMING SEQUENCE CONTROL CIRCUIT, TIMING SEQUENCE CONTROL METHOD, AND SEMICONDUCTOR MEMORY - A simplified explanation of the abstract
This abstract first appeared for US patent application 18169159 titled 'TIMING SEQUENCE CONTROL CIRCUIT, TIMING SEQUENCE CONTROL METHOD, AND SEMICONDUCTOR MEMORY
Simplified Explanation
The patent application describes a timing sequence control circuit that includes a signal transmission module and a timing sequence compensation module.
- The signal transmission module receives an initial sampling signal and generates a sampling signal.
- The timing sequence compensation module includes a compensation capacitor and is connected to the signal transmission module.
- The timing sequence compensation module receives an adjustable supply voltage and adjusts the compensation delay of the initial sampling signal based on the supply voltage and the compensation capacitor.
- The purpose of the compensation delay adjustment is to ensure that the time difference between the sampling signal and the to-be-sampled Data (DQ) signal meets a preset requirement.
Original Abstract Submitted
A timing sequence control circuit includes: a signal transmission module and a timing sequence compensation module, and the timing sequence compensation module is connected with the signal transmission module. Herein, the signal transmission module is configured to receive an initial sampling signal and transmit the initial sampling signal to generate a sampling signal. The timing sequence compensation module at least includes a compensation capacitor and is configured to receive an adjustable supply voltage, and perform compensation delay adjustment on the initial sampling signal according to the supply voltage and the compensation capacitor, so that the time difference between the sampling signal and a to-be-sampled Data (DQ) signal meets a preset requirement.
