Texas Instruments Incorporated patent applications on September 5th, 2024
Patent Applications by Texas Instruments Incorporated on September 5th, 2024
Texas Instruments Incorporated: 25 patent applications
Texas Instruments Incorporated has applied for patents in the areas of G06F9/30 (3), G06F9/345 (2), H02M3/155 (2), H02M3/158 (2), G06F11/10 (2) H03K17/08 (2), G01R31/52 (1), H02M3/155 (1), H04N19/86 (1), H04N19/61 (1)
With keywords such as: terminal, coupled, circuit, circuitry, transistor, power, data, output, stream, and current in patent application abstracts.
Patent Applications by Texas Instruments Incorporated
Inventor(s): Weiyu Shen of Shanghai (CN) for texas instruments incorporated, Douglas A Roberson of Royse City TX (US) for texas instruments incorporated, Rong Rong of Shanghai (CN) for texas instruments incorporated, Shurong Xia of Plano TX (US) for texas instruments incorporated
IPC Code(s): G01R31/52, H02H1/00, H03F1/52, H04R29/00
CPC Code(s): G01R31/52
Abstract: example systems, apparatus, articles of manufacture, and methods are disclosed to implement speaker short to power and ground diagnostics for amplifier circuits. an example circuit disclosed herein includes short detection circuitry having an input adapted to be coupled to an output of an amplifier, and an output, to sense an output current from the output of the amplifier and filter a signal corresponding to the output current from the output of the amplifier to measure a direct current (dc) offset associated with the output current, wherein the short detection circuitry output indicates a short at the output of the amplifier based on the dc offset.
Inventor(s): Sandeep RAO of Bengaluru (IN) for texas instruments incorporated, Anand DABAK of Plano TX (US) for texas instruments incorporated
IPC Code(s): G01S13/34, G01S7/02
CPC Code(s): G01S13/34
Abstract: a non-transitory computer-readable storage device stores machine instructions. when executed by one or more processors, the machine instructions cause the one or more processors to determine a first inter-chirp time with respect to a first series of chirps; and determine a second inter-chirp time with respect to a second series of chirps, in which the second inter-chirp time is different than the first inter-chirp time and is based on the first inter-chirp time and a chirp dither value. in another implementation, an oscillator receives chirp configuration signals, which contain the inter-chirp times, and generate the first and second series of chirps with the first and second inter-chirp times, respectively. transmitter circuitry, coupled to the oscillator, transmits each of the first and second series of chirps with the respective inter-chirp time.
Inventor(s): Zhongyan Sheng of Allen TX (US) for texas instruments incorporated
IPC Code(s): G02B27/01, G02B13/00
CPC Code(s): G02B27/0172
Abstract: a system includes an illumination module configured to produce illumination light and a prism. the system also includes relay optics optically coupled between the illumination module and the prism, the relay optics having a first surface, a second surface, and a third surface. the first surface is configured to reflect the illumination light to produce first reflected light, the second surface is configured to reflect the first reflected light to produce second reflected light, the third surface is configured to reflect the second reflected light to produce third reflected light, and the second surface is configured to transmit the third reflected light to produce transmitted light towards the prism. additionally, the system includes a spatial light modulator (slm) optically coupled to the prism. the prism is configured to direct the transmitted light towards the slm, and the slm is configured to produce modulated light based on the transmitted light.
Inventor(s): Lokesh Kumar Botcha of Bangalore (IN) for texas instruments incorporated, Abhijit Anant Patki of Bangalore (IN) for texas instruments incorporated
IPC Code(s): G05B19/18
CPC Code(s): G05B19/188
Abstract: an example apparatus includes a register, a memory to store reconfiguration data associated with the register, and register control circuitry. the example register control circuitry is to determine whether the memory includes the reconfiguration data corresponding to a trigger event experienced by state machine circuitry. additionally, the example register control circuitry is to, based on determining that the memory includes the reconfiguration data corresponding to the trigger event, reconfigure the register identified in the reconfiguration data with a value included in the reconfiguration data.
Inventor(s): Pauline Poyun Wang of Richardson TX (US) for texas instruments incorporated, Juha Tapani Pennanen of Oulu (FI) for texas instruments incorporated
IPC Code(s): G06F1/3206, G06F1/26, G06F1/3215, G06F1/3234
CPC Code(s): G06F1/3206
Abstract: methods and apparatus for power management of embedded devices are provided. an example apparatus includes a primary power management integrated circuit (pmic) to communicate with an embedded system to determine a power state. the example primary pmic is to include a first power state sequence controller and a first power supply controller. the example first power state sequence controller is to drive a first power supply controller according to the power state. the example first power supply controller is to activate a first set of rails to apply power to the embedded system. the example apparatus includes a secondary pmic including a second power state sequence controller and a second power supply controller. the example second power sequence controller is to drive a second power supply controller according to the power state. the example second power supply controller is to activate a second set of rails to apply power to the embedded system.
Inventor(s): Joseph Raymond Michael Zbiciak of San Jose CA (US) for texas instruments incorporated
IPC Code(s): G06F9/30, G06F5/06, G06F9/32, G06F9/345, G06F9/38, G06F11/00, G06F11/10, G06F12/0875, G06F12/0897
CPC Code(s): G06F9/3016
Abstract: a stream of data is accessed from a memory system by an autonomous memory access engine, converted on the fly by the memory access engine, and then presented to a processor for data processing. a portion of a lookup table (lut) containing converted data elements is preloaded into a lookaside buffer associated with the memory access engine. as the stream of data elements is fetched from the memory system each data element in the stream of data elements is replaced with a respective converted data element obtained from the lut in the lookaside buffer according to a content of each data element to thereby form a stream of converted data elements. the stream of converted data elements is then propagated from the memory access engine to a data processor.
Inventor(s): Timothy Anderson of University Park TX (US) for texas instruments incorporated, Joseph Zbiciak of San Jose CA (US) for texas instruments incorporated
IPC Code(s): G06F9/48, G06F9/30, G06F9/345, G06F9/38, G06F15/76
CPC Code(s): G06F9/485
Abstract: a streaming engine employed in a digital data processor specifies a fixed read only data stream recalled memory. streams are started by one of two types of stream start instructions. a stream start ordinary instruction specifies a register storing a stream start address and a register of storing a stream definition template which specifies stream parameters. a stream start short-cut instruction specifies a register storing a stream start address and an implied stream definition template. a functional unit is responsive to a stream operand instruction to receive at least one operand from a stream head register. the stream template supports plural nested loops with short-cut start instructions limited to a single loop. the stream template supports data element promotion to larger data element size with sign extension or zero extension. a set of allowed stream short-cut start instructions includes various data sizes and promotion factors.
Inventor(s): Naveen BHORIA of Plano TX (US) for texas instruments incorporated, Timothy David ANDERSON of University Park TX (US) for texas instruments incorporated, Pete HIPPLEHEUSER of Murphy TX (US) for texas instruments incorporated
IPC Code(s): G06F12/128, G06F9/30, G06F9/54, G06F11/10, G06F12/02, G06F12/0802, G06F12/0804, G06F12/0806, G06F12/0811, G06F12/0815, G06F12/0817, G06F12/0853, G06F12/0855, G06F12/0864, G06F12/0884, G06F12/0888, G06F12/0891, G06F12/0895, G06F12/0897, G06F12/12, G06F12/121, G06F12/126, G06F12/127, G06F13/16, G06F15/80, G11C5/06, G11C7/10, G11C7/22, G11C29/42, G11C29/44
CPC Code(s): G06F12/128
Abstract: a caching system including a first sub-cache, a second sub-cache, coupled in parallel with the first sub-cache, for storing cache data evicted from the first sub-cache and write-memory commands that are not cached in the first sub-cache, and a cache controller configured to receive two or more cache commands, determine a conflict exists between the received two or more cache commands, determine a conflict resolution between the received two or more cache commands, and sending the two or more cache commands to the first sub-cache and the second sub-cache.
Inventor(s): Kedar Satish CHITNIS of Bengaluru (IN) for texas instruments incorporated, Mihir Narendra MODY of Bengaluru (IN) for texas instruments incorporated, Amritpal Singh MUNDRA of Allen TX (US) for texas instruments incorporated, Yashwant DUTT of Bengaluru (IN) for texas instruments incorporated, Gregory Raymond SHURTZ of Houston TX (US) for texas instruments incorporated, Robert John TIVY of Ojai CA (US) for texas instruments incorporated
IPC Code(s): G06F21/54, G06F9/48, G06F21/55, G06F21/79
CPC Code(s): G06F21/54
Abstract: devices, systems and techniques for implementing freedom from interference (ffi) access rules. in an example, a device includes a set of primary components, a set of secondary components, and an interconnected coupled between the two sets of components. each primary component of the set of primary components has an access identifier, among multiple access attributes, and an access attribute, among multiple access modes. each secondary component of the set of secondary components is protected by a firewall. each firewall is configured to specify, for each specific combination of an access identifier and access attribute, whether access to the associated secondary component is permitted and what type of access is permitted.
Inventor(s): Sylvester Ankamah-Kusi of McKinney TX (US) for texas instruments incorporated, Yiqi Tang of Allen TX (US) for texas instruments incorporated, Rajen Manicon Murugan of Dallas TX (US) for texas instruments incorporated, Sreenivasan K. Koduri of Dallas TX (US) for texas instruments incorporated
IPC Code(s): H01L23/498, H01L21/48, H01L21/683, H01L23/00
CPC Code(s): H01L23/49838
Abstract: an electronic device includes a multilevel package substrate with first and second levels extending in planes of first and second directions and spaced apart from one another along a third direction, the first level having a first side with landing areas spaced apart from one another along the first direction. the multilevel package substrate includes a conductive structure having first and second ends and conductive portions in the first and second levels that provide a conductive path along the first direction from the landing areas toward the second end, where the conductive structure includes indents that extend into the conductive portions in the first level, the indents spaced apart from one another along the first direction and positioned along the first direction between respective pairs of the landing areas.
20240297112. PASSIVE COMPONENT MODULE_simplified_abstract_(texas instruments incorporated)
Inventor(s): Sylvester Ankamah-Kusi of Dallas TX (US) for texas instruments incorporated, Rajen Murugan of Dallas TX (US) for texas instruments incorporated, Harshpreet Bakshi of Dallas TX (US) for texas instruments incorporated, Vivek Sridharan of Dallas TX (US) for texas instruments incorporated, Ruben Rolda of Plano TX (US) for texas instruments incorporated
IPC Code(s): H01L23/50, H01C1/14, H01C7/00, H01G4/012, H01G4/33, H01L23/552, H01L25/18, H01L27/01
CPC Code(s): H01L23/50
Abstract: a passive component module includes opposite first and second sides, a base extending to the second side, and a redistribution layer structure extending between the base and the first side, the redistribution layer structure including: a passive electronic component with a first component terminal and a second component terminal; a conductive metal trace that forms at least a portion of the passive electronic component; a dielectric layer abutting a portion of the conductive metal trace; a first terminal exposed along the first side and electrically coupled to the first component terminal; and a second terminal spaced apart from the first terminal and exposed along the first side, the second terminal electrically coupled to the second component terminal.
Inventor(s): Meysam Moallem of Plano TX (US) for texas instruments incorporated
IPC Code(s): H01Q1/22, H01L27/02, H01Q1/24, H01Q23/00
CPC Code(s): H01Q1/2283
Abstract: integrated circuit packages are provided. in an example integrated circuit package, a first substrate includes a set of conductor layers including first and second conductor layers, and at least one dielectric layer disposed between the first and second conductor layers; antennas disposed in the first conductor layer. a ground plane is disposed in the second conductor layer, and a set of vias is coupled between the antennas and the ground plane. a second substrate having a first side is coupled to the first substrate via a first set of package connectors. an integrated circuit die is disposed between the first and second substrates and has a side that is coupled to the set of conductor layers. a second set of package connectors coupled to a second side of the second substrate.
Inventor(s): Amrutheshwara KV of Bangalore (IN) for texas instruments incorporated, Preetam Tadeparthy of Bangalore (IN) for texas instruments incorporated, Vikas Lakhanpal of Bangalore (IN) for texas instruments incorporated, Vikram Gakhar of Bangalore (IN) for texas instruments incorporated, Sreelakshmi S of Bangalore (IN) for texas instruments incorporated
IPC Code(s): H02M1/00, H02M3/158
CPC Code(s): H02M1/0025
Abstract: provided herein are various enhancements for voltage regulators and associated control schemes that provide power to fast transient load circuitry. in one example, a power controller includes a transient detection circuit configured to monitor a change in timing among pulse signals associated with voltage conversion phases supplying current to a load circuit. the transient detection circuit is configured to identify a transient event condition corresponding to a change in current demand of the load circuit, and responsively output an indication of the transient event condition.
Inventor(s): Manojit Chakraborty of Bangalore (IN) for texas instruments incorporated, Rejin Kanjavalappil Raveendranath of Bangalore (IN) for texas instruments incorporated
IPC Code(s): H02M3/155
CPC Code(s): H02M3/155
Abstract: a circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor. a first terminal of the second transistor is coupled to a control terminal of the first transistor. a second terminal of the second transistor is coupled to a second terminal of the first transistor. a first terminal of the third transistor is coupled to a voltage supply terminal. a second terminal of the third transistor and a first terminal of the fourth transistor are coupled to a control terminal of the second transistor. a second terminal of the fourth transistor is coupled to the second terminal of the second transistor. a first terminal of the fifth transistor is coupled to a first terminal of the first transistor. a second terminal of the fifth transistor is coupled to a control terminal of the fourth transistor.
Inventor(s): Rejin Kanjavalappil Raveendranath of Bangalore (IN) for texas instruments incorporated, Manojit Chakraborty of Bangalore (IN) for texas instruments incorporated
IPC Code(s): H02M3/157, H02M1/14, H03F3/183
CPC Code(s): H02M3/157
Abstract: a circuit including a digital-to-analog converter (dac) having a first terminal and a second terminal. the circuit also includes a first diode having a first terminal coupled to the second terminal of the dac and having a second terminal coupled to the first terminal of the dac. a comparator has a first terminal and a second terminal. a second diode has a first terminal coupled to the second terminal of the dac and has a second terminal coupled to the second terminal of the comparator. a voltage-to-current converter (v2i) has a terminal. a resistor has a first terminal coupled to the second terminal of the second diode and has a second terminal coupled to the terminal of the v2i converter.
Inventor(s): Fangli Ge of Shanghai (CN) for texas instruments incorporated, Luyang He of Nanjing (CN) for texas instruments incorporated, Ding Yan of Dallas TX (US) for texas instruments incorporated
IPC Code(s): H02M3/158, H02M1/32, H03K3/037, H03K5/24
CPC Code(s): H02M3/1582
Abstract: a voltage converter includes an amplifier, a voltage-to-current (vtoi) converter circuit, a current mirror, a slope generation circuit, and a transistor. the amplifier has an amplifier output. the vtoi converter circuit has a vtoi input and a vtoi output. the vtoi input is coupled to the amplifier output. the current mirror has a current mirror input and a current mirror output. the current mirror input is coupled to the vtoi output. the slope generation circuit has an input coupled to the current mirror input. the transistor is coupled between the amplifier output and a reference terminal. the transistor has a control input coupled to the current mirror output.
Inventor(s): Jawaharlal Tangudu of Bangalore (IN) for texas instruments incorporated, Goutham Ramesh of Bangalore (IN) for texas instruments incorporated, Sarma Sundareswara Gunturi of Bangalore (IN) for texas instruments incorporated, Harsh Garg of Delhi (IN) for texas instruments incorporated, Jaiganesh Balakrishnan of Bangalore (IN) for texas instruments incorporated, Mathews John of Bangalore (IN) for texas instruments incorporated, Sashidharan Venkatraman of Bangalore (IN) for texas instruments incorporated, Sanjay Pennam of Visakhapatnam (IN) for texas instruments incorporated
IPC Code(s): H03F1/32, H03F3/21
CPC Code(s): H03F1/3241
Abstract: an example method includes switching a first multiplexer circuit associated with first delay circuitry from (a) a first sub-lookup table (lut) of a first lut of digital pre-distortion (dpd) corrector circuitry to (b) a first corresponding sub-lut of a second lut of the dpd corrector circuitry, the first sub-lut associated with the first delay circuitry, the second lut storing updated values to compensate for non-linearity of power amplifier circuitry of a transmitter including the dpd corrector circuitry. the method includes, based on a value of a counter being equal to a difference between (1) a first delay of the first delay circuitry and (2) a second delay of second delay circuitry, switching a second multiplexer circuit associated with the second delay circuitry from (a) a second sub-lut of the first lut to (b) a second corresponding sub-lut of the second lut, the second sub-lut associated with the second delay circuitry.
20240297627. TUNABLE TRANSCONDUCTOR_simplified_abstract_(texas instruments incorporated)
Inventor(s): Hariharan SRINIVASAN of Chennai (IN) for texas instruments incorporated, Rajavelu THINAKARAN of Bangalore (IN) for texas instruments incorporated
IPC Code(s): H03F3/45, G01R31/28, H03F1/56
CPC Code(s): H03F3/45475
Abstract: in examples, a circuit includes a first and second resistors, a programmable impedance circuit, an amplifier, and a current mirror. the first resistor has a first terminal coupled to a vin terminal, and a second terminal. the second resistor has a first terminal coupled to the second terminal of the first resistor, and a second terminal coupled to a ground terminal. the programmable impedance circuit has a first terminal coupled to the second terminal of the first resistor, a tuning input, and a third terminal. the amplifier has an inverting input coupled to the ground terminal, a non-inverting input coupled to the third terminal of the programmable impedance circuit, and an output terminal. the current mirror has a first terminal coupled to the output terminal of the amplifier, a second terminal coupled to the third terminal of the programmable impedance circuit, and a third terminal coupled to an iout terminal.
Inventor(s): Trilok Kamagond of Bangalore (IN) for texas instruments incorporated, Sumantra Seth of Bangalore (IN) for texas instruments incorporated
IPC Code(s): H03K17/08, H02M3/155
CPC Code(s): H03K17/08
Abstract: methods, apparatus, systems, and articles of manufacture are disclosed corresponding to current limit circuitry with controlled current variation. an example circuit includes a voltage regulator configured to control a first transistor to regulate a supply voltage to a regulated voltage; and current limit circuitry configured to enable a second transistor to lower an output current when a voltage at a control terminal of the first transistor satisfies a threshold.
Inventor(s): Shaik BASHA of Bengaluru (IN) for texas instruments incorporated, Rejin KANJAVALAPPIL RAVEENDRANATH of Bengaluru (IN) for texas instruments incorporated, Asish DAS of Bengaluru (IN) for texas instruments incorporated
IPC Code(s): H03K17/08
CPC Code(s): H03K17/08
Abstract: a circuit includes a driver circuit. the driver circuit includes a power stage and an overcurrent control circuit. the power stage includes an output switch. the overcurrent control circuit includes a switch control circuitry and overcurrent detection circuitry. the switch control circuitry is configured to: receive a first control signal; and provide a second control signal to a control terminal of the output switch responsive to a delay interval relative to the first control signal and overcurrent detection results obtained by the overcurrent detection circuitry during the delay interval.
Inventor(s): Ramanuja Vedantham of Allen TX (US) for texas instruments incorporated, Jiun-Ren Lin of Pittsburgh PA (US) for texas instruments incorporated, Xiaolin Lu of Plano TX (US) for texas instruments incorporated
IPC Code(s): H04L45/00, H04L45/12, H04W40/12
CPC Code(s): H04L45/70
Abstract: devices, systems, and computer-readable mediums are provided for dynamically switching networks in a multi-network arrangement. a system includes multiple networks; and a node common to the multiple networks. the node includes network rating circuitry configured to determine and maintain a confidence rating value on each network of multiple networks; retransmission circuitry configured to determine a maximum number of retransmission attempts allowed on each network of the multiple networks; and network selection circuitry configured to select, based on the confidence rating values of the multiple networks, a first network of the multiple networks for transmitting a packet.
Inventor(s): Madhukar Budagavi of Plano TX (US) for texas instruments incorporated
IPC Code(s): H04N19/176, H04N19/13, H04N19/167, H04N19/463, H04N19/80
CPC Code(s): H04N19/176
Abstract: a method for adaptive loop filtering is provided that includes determining a coefficient value for each coefficient position of an adaptive loop filter, applying the adaptive loop filter to at least a portion of a reconstructed picture using the coefficient values, and entropy encoding coefficient values into a compressed bit stream using predetermined short binary codes, wherein the short binary code used depends on the coefficient position of the coefficient value.
Inventor(s): Minhua Zhou of Plano TX (US) for texas instruments incorporated
IPC Code(s): H04N19/61, H04N19/119, H04N19/157, H04N19/176
CPC Code(s): H04N19/61
Abstract: a method and apparatus for a low complexity transform unit partitioning structure for high efficiency video coding (hevc). the method includes determining prediction unit size of a coding unit, and setting the size of transform unit size of y, u and v according to the prediction unit size of the coding unit.
Inventor(s): Woo-Shik Kim of San Diego CA (US) for texas instruments incorporated, Do-Kyoung Kwon of Allen TX (US) for texas instruments incorporated, Minhua Zhou of San Diego CA (US) for texas instruments incorporated
IPC Code(s): H04N19/86, H04N19/117, H04N19/186, H04N19/463, H04N19/70, H04N19/80, H04N19/82, H04N19/91
CPC Code(s): H04N19/86
Abstract: techniques for signaling of sample adaptive offset (sao) information that may reduce the coding rate for signaling such information in the compressed bit stream are provided. more specifically, techniques are provided that allow sao information common to two or more of the color components to be signaled using one or more syntax elements (flags or indicators) representative of the common information. these techniques reduce the need to signal sao information separately for each color component.
Inventor(s): Yuval MATAR of HOD HASHARON (IL) for texas instruments incorporated, Yaron ALPERT of Hod Hasharon (IL) for texas instruments incorporated
IPC Code(s): H04W74/0816, H04L1/00, H04L5/00, H04W72/044, H04W74/08
CPC Code(s): H04W74/0816
Abstract: in an example, a method includes obtaining, in a probing wi-fi device a transmit opportunity (txop) on a wi-fi channel. the method also includes transmitting a probe packet from the probing wi-fi device to a receiving wi-fi device during the txop with a first antenna. the method includes receiving first feedback responsive to transmitting the probe packet with the first antenna. the method also includes transmitting the probe packet from the probing wi-fi device to the receiving wi-fi device during the txop with a second antenna. the method includes receiving second feedback responsive to transmitting the probe packet with the second antenna. the method also includes setting, by the probing wi-fi device, a transmission parameters set and a selected antenna based at least in part on the first feedback or the second feedback.
Texas Instruments Incorporated patent applications on September 5th, 2024
- Texas Instruments Incorporated
- G01R31/52
- H02H1/00
- H03F1/52
- H04R29/00
- CPC G01R31/52
- Texas instruments incorporated
- G01S13/34
- G01S7/02
- CPC G01S13/34
- G02B27/01
- G02B13/00
- CPC G02B27/0172
- G05B19/18
- CPC G05B19/188
- G06F1/3206
- G06F1/26
- G06F1/3215
- G06F1/3234
- CPC G06F1/3206
- G06F9/30
- G06F5/06
- G06F9/32
- G06F9/345
- G06F9/38
- G06F11/00
- G06F11/10
- G06F12/0875
- G06F12/0897
- CPC G06F9/3016
- G06F9/48
- G06F15/76
- CPC G06F9/485
- G06F12/128
- G06F9/54
- G06F12/02
- G06F12/0802
- G06F12/0804
- G06F12/0806
- G06F12/0811
- G06F12/0815
- G06F12/0817
- G06F12/0853
- G06F12/0855
- G06F12/0864
- G06F12/0884
- G06F12/0888
- G06F12/0891
- G06F12/0895
- G06F12/12
- G06F12/121
- G06F12/126
- G06F12/127
- G06F13/16
- G06F15/80
- G11C5/06
- G11C7/10
- G11C7/22
- G11C29/42
- G11C29/44
- CPC G06F12/128
- G06F21/54
- G06F21/55
- G06F21/79
- CPC G06F21/54
- H01L23/498
- H01L21/48
- H01L21/683
- H01L23/00
- CPC H01L23/49838
- H01L23/50
- H01C1/14
- H01C7/00
- H01G4/012
- H01G4/33
- H01L23/552
- H01L25/18
- H01L27/01
- CPC H01L23/50
- H01Q1/22
- H01L27/02
- H01Q1/24
- H01Q23/00
- CPC H01Q1/2283
- H02M1/00
- H02M3/158
- CPC H02M1/0025
- H02M3/155
- CPC H02M3/155
- H02M3/157
- H02M1/14
- H03F3/183
- CPC H02M3/157
- H02M1/32
- H03K3/037
- H03K5/24
- CPC H02M3/1582
- H03F1/32
- H03F3/21
- CPC H03F1/3241
- H03F3/45
- G01R31/28
- H03F1/56
- CPC H03F3/45475
- H03K17/08
- CPC H03K17/08
- H04L45/00
- H04L45/12
- H04W40/12
- CPC H04L45/70
- H04N19/176
- H04N19/13
- H04N19/167
- H04N19/463
- H04N19/80
- CPC H04N19/176
- H04N19/61
- H04N19/119
- H04N19/157
- CPC H04N19/61
- H04N19/86
- H04N19/117
- H04N19/186
- H04N19/70
- H04N19/82
- H04N19/91
- CPC H04N19/86
- H04W74/0816
- H04L1/00
- H04L5/00
- H04W72/044
- H04W74/08
- CPC H04W74/0816
