Texas Instruments Incorporated patent applications on September 26th, 2024
Patent Applications by Texas Instruments Incorporated on September 26th, 2024
Texas Instruments Incorporated: 29 patent applications
Texas Instruments Incorporated has applied for patents in the areas of H03M1/12 (3), G06F13/38 (2), G06F13/40 (2), G06F9/30 (2), H03K3/037 (2) G01R15/207 (1), H02M3/155 (1), H04W72/21 (1), H04W24/10 (1), H04N19/176 (1)
With keywords such as: current, coupled, terminal, output, circuit, input, data, signal, control, and transistor in patent application abstracts.
Patent Applications by Texas Instruments Incorporated
Inventor(s): Dok Won Lee of MOUNTAIN VIEW CA (US) for texas instruments incorporated, Jo Bito of Fresno CA (US) for texas instruments incorporated, Keith Ryan Green of MCKINNEY TX (US) for texas instruments incorporated
IPC Code(s): G01R15/20, H01L23/495, H10B61/00, H10N52/00, H10N52/80, H10N59/00
CPC Code(s): G01R15/207
Abstract: in one example, a device comprises a lead frame, a semiconductor die, a spacer, and a magnetic concentrator. the lead frame comprises a conductor. the spacer is between the semiconductor die and the conductor. the magnetic concentrator overlaps at least partially with the conductor.
Inventor(s): Tanmay Neema of Bangalore (IN) for texas instruments incorporated, Rajavelu Thinakaran of BANGALORE (IN) for texas instruments incorporated, Gautam Salil Nandi of Bangalore (IN) for texas instruments incorporated, Vishal Monteiro of BANGALORE (IN) for texas instruments incorporated, Deepak Kumar Meher of Bangalore (IN) for texas instruments incorporated
IPC Code(s): G01R31/28
CPC Code(s): G01R31/2834
Abstract: in described examples, a test control circuit includes a subsystem and a transition control circuit. the subsystem outputs test signals to, and receives and measures response signals of, a device under test (dut). the transition control circuit operates the test control circuit in response to a first operational state information indicating a first mode and a first set of configuration settings; receives a transition trigger signal and a second operational state information indicating a second mode and a second set of configuration settings; and, by performing allowed mode changes and in response to receiving the transition trigger signal, transitions the test control circuit to operating in response to the second operational state information. allowed mode changes are restricted to: from a dut driving mode to a dut non-driving mode, from a dut non-driving mode to another dut non-driving mode, or from a dut non-driving mode to a dut driving mode.
20240319274. 3D STACKED DIE TEST ARCHITECTURE_simplified_abstract_(texas instruments incorporated)
Inventor(s): Lee D. Whetsel of Parker TX (US) for texas instruments incorporated
IPC Code(s): G01R31/3185, G01R31/317, G01R31/3177
CPC Code(s): G01R31/318555
Abstract: this disclosure describes a test architecture that supports a common approach to testing individual die and dies in a 3d stack arrangement. the test architecture uses an improved tap design to facilitate the testing of parallel test circuits within the die.
Inventor(s): Yicheng Zhou of Shanghai (CN) for texas instruments incorporated, Xiaodong Li of Shanghai (CN) for texas instruments incorporated, Kangcheng Xu of Shanghai (CN) for texas instruments incorporated
IPC Code(s): G01R31/374, G01R31/3842, G01R35/00, H03M1/12
CPC Code(s): G01R31/374
Abstract: various examples disclosed herein relate to current sensing via current sensing circuitry, and more particularly, to calibrating current sensing circuitry to dynamically detect current ranges across a load. in an example embodiment, a microcontroller unit (mcu) is provided herein that includes a processor and current sensing circuitry coupled to the processor. the current sensing circuitry of the mcu is configured to measure voltages associated with a load. the processor of the mcu is configured to obtain the measured voltages from the current sensing circuitry, identify a temperature drift of the current sensing circuitry that exceeds a threshold value, update parameters with which to determine a current associated with the load based on the temperature drift, and determine the current associated with the load based on the updated parameters and the measured voltages.
Inventor(s): Borja Martinez Huerta of Sant Cugat (ES) for texas instruments incorporated, Guillem Boquet Pujadas of Mataró (ES) for texas instruments incorporated, Xavier Vilajosana Guillen of Cardedeu (ES) for texas instruments incorporated, Anand Ganesh Dabak of Plano TX (US) for texas instruments incorporated, Kaichien Tsai of Allen TX (US) for texas instruments incorporated, Jianwei Zhou of Allen TX (US) for texas instruments incorporated, Danil Shalumov of Or Aqiva (IL) for texas instruments incorporated
IPC Code(s): G01S5/02, G01S5/04, H04W64/00
CPC Code(s): G01S5/0244
Abstract: in an example method of target position estimation, the method includes calculating initial estimated positions of a target transmitter. each of the initial estimated positions is based on an angle of arrival estimate received from a locator. the method includes generating an error projection associated with each of the initial estimated positions. the error projection is based on azimuth and elevation error characteristics of the locator associated with the initial estimated position. the method includes creating a select group of the locators based on overlaps of the error projections, wherein the select group of locators comprises a subset of the locators. the method includes calculating a refined estimate of the position of the target transmitter based on the initial estimated positions associated with the select group of locators.
Inventor(s): Duc Bui of Grand Prairie TX (US) for texas instruments incorporated, Peter Richard Dent of Bournemouth (GB) for texas instruments incorporated, Timothy D. Anderson of University Park TX (US) for texas instruments incorporated
IPC Code(s): G06F9/30
CPC Code(s): G06F9/3013
Abstract: a method to compare first and second source data in a processor in response to a vector maximum with indexing instruction includes specifying first and second source registers containing first and second source data, a destination register storing compared data, and a predicate register. each of the registers includes a plurality of lanes. the method includes executing the instruction by, for each lane in the first and second source register, comparing a value in the lane of the first source register to a value in the corresponding lane of the second source register to identify a maximum value, storing the maximum value in a corresponding lane of the destination register, asserting a corresponding lane of the predicate register if the maximum value is from the first source register, and de-asserting the corresponding lane of the predicate register if the maximum value is from the second source register.
Inventor(s): Mark Edward Wentroble of Plano TX (US) for texas instruments incorporated, Anant Shankar Kamath of Bengaluru (IN) for texas instruments incorporated, Rakesh Hariharan of Bengaluru (IN) for texas instruments incorporated, Prajwala P of Bengaluru (IN) for texas instruments incorporated, Suzanne Mary Vining of Plano TX (US) for texas instruments incorporated
IPC Code(s): G06F9/4401, G06F1/3215, G06F13/38, G06F13/42
CPC Code(s): G06F9/4411
Abstract: a serial bus repeater includes first and second ports adapted to be coupled to respective devices. a first termination resistor network couples to the first port. a second termination resistor network couples to the second port. a squelch detect circuit couples to the first bus port and is configured to detect activity on the first bus and to generate a squelch signal responsive to detection of activity on the first port. a first state machine is configured to: determine an elapsed time during which the squelch signal indicates activity on the first port; determine that the elapsed time exceeds a first threshold; and, responsive to the determination that the elapsed time exceeds the first threshold, assert configuration signals to reconfigure the first and second termination resistor networks.
Inventor(s): Mihir Narendra MODY of Bengaluru (IN) for texas instruments incorporated, Kedar Satish CHITNIS of Bengaluru (IN) for texas instruments incorporated, Kumar DESAPPAN of Bengaluru (IN) for texas instruments incorporated, David SMITH of Allen TX (US) for texas instruments incorporated, Pramod Kumar SWAMI of Bengaluru (IN) for texas instruments incorporated, Shyam JAGANNATHAN of Bengaluru (IN) for texas instruments incorporated
IPC Code(s): G06F9/50, G06F9/455, G06F12/00, G06F12/02, G06N3/02, G06N3/10, G06N20/00
CPC Code(s): G06F9/5016
Abstract: techniques for executing machine learning (ml) models including receiving an indication to run an ml model on a processing core; receiving a static memory allocation for running the ml model on the processing core; determining that a layer of the ml model uses more memory than the static memory allocated; transmitting, to a shared memory, a memory request for blocks of the shared memory; receiving an allocation of the requested blocks; running the layer of the ml model using the static memory and the range of memory addresses; and outputting results of running the layer of the ml model.
Inventor(s): Saya Goud Langadi of Bangalore (IN) for texas instruments incorporated, David Peter Foley of Sugar Land TX (US) for texas instruments incorporated
IPC Code(s): G06F11/10, G06F11/07, G06F11/30, G06F13/16
CPC Code(s): G06F11/1068
Abstract: methods, apparatus, systems, and articles of manufacture are disclosed to determine memory access integrity based on feedback from memory. an example apparatus includes an access reconstruction controller including an output, a first input configured to be coupled to memory, and a second input configured to be coupled to a memory signal generator; a comparator including a first input coupled to the output of the access reconstruction controller, a second input configured to be coupled to an arbiter, and an output configured to be coupled to the arbiter; and a data integrity monitor including an input coupled to the second input of the comparator and configured to be coupled to the arbiter and an output coupled to the output of the comparator and configured to be coupled to the arbiter.
Inventor(s): Joseph Zbiciak of San Jose CA (US) for texas instruments incorporated, Timothy Anderson of University Park TX (US) for texas instruments incorporated
IPC Code(s): G06F11/10, G06F9/30, G06F9/345, G06F9/38, G06F11/00, G06F11/14, G06F12/0817, G06F12/0875, G06F12/0897, G06F13/38, G06F13/40
CPC Code(s): G06F11/1076
Abstract: disclosed embodiments relate to a streaming engine employed in, for example, a digital signal processor. a fixed data stream sequence including plural nested loops is specified by a control register. the streaming engine includes an address generator producing addresses of data elements and a steam head register storing data elements next to be supplied as operands. the streaming engine fetches stream data ahead of use by the central processing unit core in a stream buffer. parity bits are formed upon storage of data in the stream buffer which are stored with the corresponding data. upon transfer to the stream head register a second parity is calculated and compared with the stored parity. the streaming engine signals a parity fault if the parities do not match. the streaming engine preferably restarts fetching the data stream at the data element generating a parity fault.
20240320154. MULTI-LEVEL CACHE SECURITY_simplified_abstract_(texas instruments incorporated)
Inventor(s): Abhijeet Ashok Chachad of Plano TX (US) for texas instruments incorporated, David Matthew Thompson of Dallas TX (US) for texas instruments incorporated, Naveen Bhoria of Plano TX (US) for texas instruments incorporated
IPC Code(s): G06F12/0811, G06F9/46, G06F12/0817, G06F12/0831, G06F12/1081, G06F12/14, G06F21/79
CPC Code(s): G06F12/0811
Abstract: an example system includes first and second level memories and first and second memory controllers respectively coupled thereto. the system also includes a shadow cache associated with the second level memory and coupled to the second memory controller, which is also coupled to the first memory controller. in response to a generated read operation that includes a secure code, the second memory controller determines whether an address of the read operation matches an address that is tagged in the shadow cache; and determine whether the secure code of the read operation matches a secure code of a cache line hit by the read operation. the second memory controller then performs one of two sets of additional operations, depending on whether or not the address of the read operation matches the address tagged in the shadow cache and whether or not the secure code of the read operation matches the secure code of the cache line.
Inventor(s): Yonghui TANG of Plano TX (US) for texas instruments incorporated, Yanli FAN of Dallas TX (US) for texas instruments incorporated
IPC Code(s): G06F13/40, G06F13/42, H03K5/1534, H03K5/24
CPC Code(s): G06F13/4022
Abstract: in an embodiment, a current source is coupled to a first current terminal of a switch, the second current terminal of which is coupled to a first data line in a communication system. an edge detector has a first input, a second input, and an output, in which the first input is coupled to a second data line in the communication system, the second input is coupled to the first data line, and the output is coupled to a control terminal of the switch. the first and second data lines may be positive and negative data lines, respectively, of the communication system.
Inventor(s): Devanathan VARADARAJAN of ALLEN TX (US) for texas instruments incorporated, Varun SINGH of PLANO TX (US) for texas instruments incorporated
IPC Code(s): G11C29/44, G11C29/16, G11C29/40
CPC Code(s): G11C29/4401
Abstract: circuits and methods are directed to repairable memory systems and memory repair processes. an example circuit includes first and second logic coupled together. the first logic receives a plurality of instances of defect data from a plurality of memories, respectively, in which each of the plurality of instances of defect data has a memory-specific format. the first logic converts each of the plurality of instances of defect data to a common format and merges the plurality instances of defect data in the common format to generate merged data. the second logic receives the merged data and determines a plurality of instances of repair data for the plurality of instances of defect data, respectively, based on the merged data.
Inventor(s): Jingjing Chen of San Jose CA (US) for texas instruments incorporated, Archana Venugopal of Mountain View CA (US) for texas instruments incorporated
IPC Code(s): H01L23/38, H01L23/532, H01L29/78
CPC Code(s): H01L23/38
Abstract: semiconductor devices including thermoelectric coolers and method of operating the semiconductor devices are described. a semiconductor device includes an soi substrate with one or more components (e.g., a transistor) generating heat during operation. the semiconductor device includes a thermoelectric cooler surrounding the transistor. the thermoelectric cooler includes a first electrode laterally surrounding the transistor, a holey silicon region laterally surrounding and contacting the first electrode, and a second electrode laterally surrounding and contacting the holey silicon region. the thermoelectric cooler, when activated, can reduce operating temperature of the transistor. in some cases, pre-cooling may be done to further reduce the operating temperature.
Inventor(s): Dong Seup Lee of McKinney TX (US) for texas instruments incorporated, Jungwoo Joh of Allen TX (US) for texas instruments incorporated
IPC Code(s): H01L29/66, H01L29/20, H01L29/40, H01L29/778
CPC Code(s): H01L29/66462
Abstract: a microelectronic device includes a gan fet on a substrate such as silicon and a buffer layer of a gan semiconductor material. the gan fet includes a contact etch stop and a stretch contact electrically connecting a source region with the contact etch stop. the contact etch stop may stretch over a p-type gan gate structure towards a drain region to form a field plate connected to the source region. the contact etch stop provides a method to connect the field plate to the source region which allows efficient area scaling of space between the source region and the p-gan gate structure. disclosed examples provide an associated process flow for forming such gan fets.
Inventor(s): RONNIE ANTONE BEAN, JR. of LENOIR CITY TN (US) for texas instruments incorporated, BENJAMIN MATTHEW MCCUE of CLINTON TN (US) for texas instruments incorporated
IPC Code(s): H02M3/155, H02J7/00, H02M1/00, H02M1/08
CPC Code(s): H02M3/155
Abstract: a circuit includes a current sensor circuit having inputs and an output. the current sensor inputs are adapted to be coupled to inductor terminals a power converter. the current sensor circuit includes a tunable time constant circuit coupled between the current sensor inputs and the current sensor output. a time constant control circuit is coupled to a tunable time constant circuit, and is configured to tune the time constant circuit responsive to the current sensor output and another signal representative of inductor current. an adjustable gain circuit has a first input coupled to the current sensor output. a direct current resistance (dcr) control circuit has an output coupled to a second input of the adjustable gain circuit, and the dcr control circuit is configured to provide a gain adjust signal at the output thereof responsive to an average current of the inductor and a current command signal for the power converter.
Inventor(s): Joseph Sankman of Dallas TX (US) for texas instruments incorporated
IPC Code(s): H03F1/42, H03F3/04, H03F3/30, H03F3/45, H03M1/12
CPC Code(s): H03F1/42
Abstract: an amplifier includes a first stage and a second stage. the first stage includes a first output and a second output. the second stage includes an output, a first transistor and a second transistor. the first transistor includes a drain coupled to the first output of the first stage, and a source coupled to the output of the second stage. the second transistor includes a drain coupled to the second output of the first stage, and a gate coupled to the output of the second stage.
Inventor(s): John Carlo Molina of Limay (PH) for texas instruments incorporated, Laura May Antoinette Dela Paz Clemente of Mabalacat City (PH) for texas instruments incorporated, Ray Fredric De Asis of Mabalcat City (PH) for texas instruments incorporated
IPC Code(s): H03H9/10, H03H3/02, H03H9/02, H03H9/05
CPC Code(s): H03H9/1042
Abstract: a semiconductor package comprises a leadframe having a die attach pad and one or more leads and a semiconductor die electrically connected to the die attach pad. a baw device is attached to the semiconductor die. a mold compound surrounds the first semiconductor die and covers portions of the leadframe and a first portion of a top surface of the semiconductor die. the mold compound has a cavity area. the mold compound does not cover the baw device or a second portion of the top surface of the semiconductor die in the cavity area. a glob top material is disposed within the cavity area. the glob top material covers the baw device and the second portion of the top of the semiconductor die.
Inventor(s): Deep BANERJEE of Bengaluru (IN) for texas instruments incorporated, Lokesh Kumar GUPTA of Bengaluru (IN) for texas instruments incorporated, Madhulatha BONU of Bengaluru (IN) for texas instruments incorporated
IPC Code(s): H03K3/017, H03K3/037, H03K17/56
CPC Code(s): H03K3/017
Abstract: an analog duty-cycle detector includes: off-time detection circuitry; on-time detection circuitry; compare circuitry; and a controller. the off-time detection circuitry includes a first transistor and a first capacitor. the on-time detection circuitry includes a second transistor and a second capacitor. the compare circuitry has a first terminal, a second terminal, and a third terminal. the first terminal of the compare circuitry is coupled to a first terminal of the first capacitor. the second terminal of the compare circuitry is coupled to a first terminal of the second capacitor. the controller has a first terminal and a second terminal. the first terminal of the controller coupled to a control terminal of the first transistor. the second terminal of the controller coupled to the control terminal of the second transistor.
20240322804. PULSE WIDTH DISTORTION CORRECTION_simplified_abstract_(texas instruments incorporated)
Inventor(s): Adam Shook of Carollton TX (US) for texas instruments incorporated
IPC Code(s): H03K5/08
CPC Code(s): H03K5/08
Abstract: an integrated circuit (ic) includes a signal detection circuit having a signal detection circuit input and a signal detection circuit output. the ic further includes a reference voltage circuit having a reference voltage circuit input and a reference voltage circuit output. the ic also includes a comparator having a first comparator input and a second comparator input. the first comparator input is coupled to the reference voltage circuit output, and the second comparator input is coupled to the signal detection circuit output. the ic includes a clamp circuit having a clamp circuit input and a clamp circuit output. the clamp circuit input is coupled to the signal detection circuit, and the clamp circuit output is coupled to the reference voltage circuit output.
Inventor(s): Rohan Sinha of Bengaluru (IN) for texas instruments incorporated, Anand Kamra of Bengaluru (IN) for texas instruments incorporated
IPC Code(s): H03K5/24, H02M3/07, H03K3/037
CPC Code(s): H03K5/2481
Abstract: a pulse generator circuit includes a charge pump having a charge pump output. a voltage divider is coupled to the charge pump output. the voltage divider has a voltage divider output. an error amplifier has a first error amplifier input and a second error amplifier input. the first error amplifier input is coupled to the voltage divider output. a dependent current source circuit has a first input coupled to the charge pump output, a second input coupled to the voltage divider output, and a third input coupled to the second error amplifier input. the dependent current source is configured to cause a current to flow from the charge pump output that is proportional to a difference between a first voltage at the voltage divider output and a second voltage at the second error amplifier input.
20240322825. PUSH-PULL BUFFER CIRCUIT_simplified_abstract_(texas instruments incorporated)
Inventor(s): Nghia Tang of Flower Mound TX (US) for texas instruments incorporated
IPC Code(s): H03K19/00, H03F3/26, H03F3/45
CPC Code(s): H03K19/0013
Abstract: a circuit includes a first transistor having a first current terminal, a second current terminal, and a control terminal, the first current terminal coupled to an output terminal, and the control terminal coupled to an input terminal, a second transistor having a first current terminal, a second current terminal, and a control terminal, the first current terminal coupled to the second current terminal of the first transistor, a third transistor having a first current terminal, a second current terminal, and a control terminal, the first current terminal coupled to the output terminal, and the control terminal coupled to the second current terminal of the second transistor, and a fourth transistor having a first current terminal and a control terminal, the first current terminal coupled to the second current terminal of the second transistor, and the control terminal coupled to the second current terminal of the third transistor.
20240322831. ADAPTIVE CLOCK SIGNAL MANAGEMENT_simplified_abstract_(texas instruments incorporated)
Inventor(s): G. Anand Kumar of Bangalore (IN) for texas instruments incorporated, Srinivasa Chakravarthy of Bangalore (IN) for texas instruments incorporated
IPC Code(s): H03L7/24, G06F1/08, G06F1/3296, H03M1/12
CPC Code(s): H03L7/24
Abstract: various embodiments disclosed herein relate to adaptive clock signal management, and more specifically to generating a clock signal at desired frequencies based on inputs to a clock subsystem for peripheral use. a clock subsystem is provided herein that comprises an oscillator configured to provide a clock signal at either a first frequency or a second frequency, and a controller coupled to the oscillator and configured to perform various functions. the controller can be configured to determine a desired frequency of the clock signal based on a state of each input of multiple inputs, wherein the multiple inputs comprise a power mode input and an analog-to-digital converter input, and provide a signal to the oscillator to produce the clock signal at the desired frequency.
20240322926. OPEN REAL-TIME ETHERNET PROTOCOL_simplified_abstract_(texas instruments incorporated)
Inventor(s): THOMAS ANTON LEYRER of GEISENHAUSEN (DE) for texas instruments incorporated, THOMAS MAUER of GAMMELSDORF (DE) for texas instruments incorporated
IPC Code(s): H04J3/06, H04L12/403, H04L12/64, H04L47/625, H04L49/90, H04L69/16
CPC Code(s): H04J3/0661
Abstract: a real-time ethernet (rte) protocol includes start-up frames originated by a master device for network initialization including a preamble, destination address (da), source address (sa), a type field, and a status field including state information that indicates a current protocol state that the ethernet network is in for the slave devices to translate for dynamically switching to one of a plurality of provided frame forwarding modes. the start-up frames include device discovery frames at power up, parameterization frames that distribute network parameters, and time synchronization frames including the master's time and unique assigned communication time slots for each slave device. after the initialization at least one data exchange frame is transmitted exclusive of sa and da including a preamble that comprises a header that differentiates between master and slave, a type field, a status field excluding the current protocol state, and a data payload.
Inventor(s): Kalpesh Laxmanbhai Rajai of Bangalore (IN) for texas instruments incorporated, Sankar Prasad Debnath of Bangalore (IN) for texas instruments incorporated, Geet Govind Modi of Bangalore (IN) for texas instruments incorporated
IPC Code(s): H04J3/06
CPC Code(s): H04J3/0664
Abstract: systems, apparatus, articles of manufacture, and methods are described for precise timestamping of an ethernet frame. in some implementations, a device may include network interface circuitry; logic circuitry configured to execute instructions to cause the logic circuitry to: determine a first delay introduced by a physical coding sublayer circuitry at a first time; adjust a first timestamp associated with a first transmission based on the first delay, the first timestamp transmitted with the first transmission; determine a second delay introduced by the physical coding sublayer circuitry at a second time, the second delay different than the first delay; and adjust a second timestamp associated with a second transmission based on the second delay, the second timestamp transmitted with the second transmission.
Inventor(s): Mihir Narendra Mody of Bengalaru (IN) for texas instruments incorporated, Niraj Nandan of Nandan (IN) for texas instruments incorporated, Hideo Tamama of San Diego CA (US) for texas instruments incorporated
IPC Code(s): H04N19/176, H04N19/117, H04N19/14, H04N19/186, H04N19/82, H04N19/86
CPC Code(s): H04N19/176
Abstract: a method of de-blocking filtering a processed video is provided. the processed video includes a plurality of blocks and each block includes a plurality of sub-blocks. a current block of the plurality of blocks includes vertical edges and horizontal edges. the processed video further includes a set of control parameters and reconstructed pixels corresponding to the current block. a boundary strength index is estimated at the vertical edges and at the horizontal edges of the current block. the set of control parameters, the reconstructed pixels corresponding to the current block and partially filtered pixels corresponding to a set of adjacent sub-blocks are loaded. the vertical edges and the horizontal edges of the current block are filtered based on the boundary strength index and the set of control parameters such that a vertical edge of the current block is filtered before filtering at least one horizontal edge of the current block.
Inventor(s): Vikram Chandrasekhar of Mountain View CA (US) for texas instruments incorporated, Runhua Chen of Plano TX (US) for texas instruments incorporated, Anthony Edet Ekpenyong of San Diego CA (US) for texas instruments incorporated
IPC Code(s): H04W24/10, H04B7/06, H04L5/00, H04W74/0833
CPC Code(s): H04W24/10
Abstract: a method and user equipment for channel state information (csi) reporting are described. the method receives a channel quality indicator request. the method determines a channel quality indicator based on a csi reference resource. the method transmits a csi report that includes the channel quality indicator via a physical uplink control channel (pucch) on an uplink subframe. the csi reference resource belongs to a subframe subset for which the csi report is sent. the csi reference resource includes overhead of demodulation reference signals according to a corresponding rank report.
Inventor(s): June Chul Roh of Allen TX (US) for texas instruments incorporated, Pierre Bertrand of Antibes (FR) for texas instruments incorporated, Srinath Hosur of Plano TX (US) for texas instruments incorporated, Vijay Pothukuchi of Allen TX (US) for texas instruments incorporated, Mohamed Farouk Mansour of Richardson TX (US) for texas instruments incorporated
IPC Code(s): H04W72/21, H03M13/00, H03M13/15, H03M13/29, H04H20/38, H04L1/00, H04L1/1812, H04W72/0446
CPC Code(s): H04W72/21
Abstract: a method for communicating over a wireless backhaul channel comprising generating a radio frame comprising a plurality of time slots, wherein each time slot comprises a plurality of symbols in time and a plurality of sub-carriers in a system bandwidth, broadcasting a broadcast channel signal comprising a transmission schedule to a plurality of remote units in a number of consecutive sub-carriers centered about a direct current (dc) sub-carrier in at least one of the time slots in the radio frame regardless of the system bandwidth, and transmitting a downlink (dl) control channel signal and a dl data channel signal to a first of the remote units, wherein the dl data channel signal is transmitted by employing a single carrier block transmission scheme comprising a discrete fourier transform (dft) spreading for frequency diversity.
Inventor(s): Gustavo Martinez of Missouri City TX (US) for texas instruments incorporated, Han Zhang of Missouri City TX (US) for texas instruments incorporated, Robert Sheehan of Grand Ridge FL (US) for texas instruments incorporated, Manish Bhardwaj of San Diego CA (US) for texas instruments incorporated
IPC Code(s): H05B45/3725, H02M1/00, H02M3/158
CPC Code(s): H05B45/3725
Abstract: four-switch buck boost power stages with reduced overshoot conditions at an output node are presented. based on a detected condition for a decrease in a quantity of the active load elements, the method includes enabling an active discharge circuit coupled to an output node of a power stage before the quantity of the active load elements is decreased. based on a detected condition for an increase in the quantity of the active load elements, the method includes activating the load elements and applying a restricted gain to the voltage conversion circuit.
Texas Instruments Incorporated patent applications on September 26th, 2024
- Texas Instruments Incorporated
- G01R15/20
- H01L23/495
- H10B61/00
- H10N52/00
- H10N52/80
- H10N59/00
- CPC G01R15/207
- Texas instruments incorporated
- G01R31/28
- CPC G01R31/2834
- G01R31/3185
- G01R31/317
- G01R31/3177
- CPC G01R31/318555
- G01R31/374
- G01R31/3842
- G01R35/00
- H03M1/12
- CPC G01R31/374
- G01S5/02
- G01S5/04
- H04W64/00
- CPC G01S5/0244
- G06F9/30
- CPC G06F9/3013
- G06F9/4401
- G06F1/3215
- G06F13/38
- G06F13/42
- CPC G06F9/4411
- G06F9/50
- G06F9/455
- G06F12/00
- G06F12/02
- G06N3/02
- G06N3/10
- G06N20/00
- CPC G06F9/5016
- G06F11/10
- G06F11/07
- G06F11/30
- G06F13/16
- CPC G06F11/1068
- G06F9/345
- G06F9/38
- G06F11/00
- G06F11/14
- G06F12/0817
- G06F12/0875
- G06F12/0897
- G06F13/40
- CPC G06F11/1076
- G06F12/0811
- G06F9/46
- G06F12/0831
- G06F12/1081
- G06F12/14
- G06F21/79
- CPC G06F12/0811
- H03K5/1534
- H03K5/24
- CPC G06F13/4022
- G11C29/44
- G11C29/16
- G11C29/40
- CPC G11C29/4401
- H01L23/38
- H01L23/532
- H01L29/78
- CPC H01L23/38
- H01L29/66
- H01L29/20
- H01L29/40
- H01L29/778
- CPC H01L29/66462
- H02M3/155
- H02J7/00
- H02M1/00
- H02M1/08
- CPC H02M3/155
- H03F1/42
- H03F3/04
- H03F3/30
- H03F3/45
- CPC H03F1/42
- H03H9/10
- H03H3/02
- H03H9/02
- H03H9/05
- CPC H03H9/1042
- H03K3/017
- H03K3/037
- H03K17/56
- CPC H03K3/017
- H03K5/08
- CPC H03K5/08
- H02M3/07
- CPC H03K5/2481
- H03K19/00
- H03F3/26
- CPC H03K19/0013
- H03L7/24
- G06F1/08
- G06F1/3296
- CPC H03L7/24
- H04J3/06
- H04L12/403
- H04L12/64
- H04L47/625
- H04L49/90
- H04L69/16
- CPC H04J3/0661
- CPC H04J3/0664
- H04N19/176
- H04N19/117
- H04N19/14
- H04N19/186
- H04N19/82
- H04N19/86
- CPC H04N19/176
- H04W24/10
- H04B7/06
- H04L5/00
- H04W74/0833
- CPC H04W24/10
- H04W72/21
- H03M13/00
- H03M13/15
- H03M13/29
- H04H20/38
- H04L1/00
- H04L1/1812
- H04W72/0446
- CPC H04W72/21
- H05B45/3725
- H02M3/158
- CPC H05B45/3725
