Texas Instruments Incorporated patent applications on September 19th, 2024
Patent Applications by Texas Instruments Incorporated on September 19th, 2024
Texas Instruments Incorporated: 26 patent applications
Texas Instruments Incorporated has applied for patents in the areas of G06F9/38 (3), G06F11/10 (2), G06F9/30 (2), H01Q9/04 (2), H03M1/10 (2) G01R1/06766 (1), H02M3/33507 (1), H04N19/86 (1), H04L69/18 (1), H04B1/7156 (1)
With keywords such as: terminal, coupled, control, signal, circuit, current, output, transistor, frequency, and configured in patent application abstracts.
Patent Applications by Texas Instruments Incorporated
Inventor(s): Rajavelu Thinakaran of Bangalore (IN) for texas instruments incorporated, Gautam Salil Nandi of Bangalore (IN) for texas instruments incorporated, Hariharan Srinivasan of Chennai (IN) for texas instruments incorporated, Rahul Shaw of Asansol (IN) for texas instruments incorporated, Abhishek Ghosh of Bangalore (IN) for texas instruments incorporated, Taras Dudar of Plano TX (US) for texas instruments incorporated
IPC Code(s): G01R1/067
CPC Code(s): G01R1/06766
Abstract: an apparatus includes a circuit including a force amplifier having an output, a resistor having a first terminal coupled to the output of the force amplifier, and a second terminal. the circuit also includes a diode clamp including a first diode having a first terminal coupled to the first terminal of the resistor, and having a second terminal coupled to the second terminal of the resistor, the first diode having a first orientation. the diode clamp also includes a second diode coupled in parallel with the first diode between the first and second terminals of the resistor, the second diode having a second orientation opposite than the first diode.
Inventor(s): Gautam Salil NANDI of Bangalore (IN) for texas instruments incorporated, Rajavelu THINAKARAN of Bangalore (IN) for texas instruments incorporated, Hariharan SRINIVASAN of Chennai (IN) for texas instruments incorporated
IPC Code(s): G01R31/28, G01R19/18, G01R35/00, H03F3/04
CPC Code(s): G01R31/2834
Abstract: in some examples, a method of performing measurement of a device under test (dut) coupled to a connector includes determining a first voltage signal representative of a current of the dut, the current flowing through the connector. the method also includes determining a second voltage signal representative of a voltage of the dut, as provided at the connector. the method also includes determining a calibration current according to the first voltage signal. the method also includes modifying measurement of the dut according to the calibration current.
Inventor(s): Charles Kasimer SESTOK, IV of Dallas TX (US) for texas instruments incorporated, David Patrick MAGEE of Allen TX (US) for texas instruments incorporated
IPC Code(s): G01R31/319, G01R31/3167, H03M1/06, H03M1/10
CPC Code(s): G01R31/31922
Abstract: a circuit comprises a driver circuit, a processing circuit, and a control circuit. the driver circuit has a first frequency control input and a driver output. the processing circuit has a sense input, a second frequency control input, and a parameter output. and the control circuit has a first frequency control output and a second frequency control output, the first frequency control output coupled to the first frequency control input, and the second frequency control output coupled to the second frequency control input.
Inventor(s): Karthik Anyam of Bengaluru (IN) for texas instruments incorporated, Preetam Charan Anand Tadeparthy of Bangalore (IN) for texas instruments incorporated, Mayank Jain of Bangalore (IN) for texas instruments incorporated, Dattatreya Baragur Suryanarayana of Bangalore (IN) for texas instruments incorporated, Charan Hemanth Kumar of Bangalore (IN) for texas instruments incorporated
IPC Code(s): G01R31/40
CPC Code(s): G01R31/40
Abstract: an example apparatus includes: a phase circuit configured to receive a pulse of a pulse width module (pwm) signal; provide, after receiving the pulse, an output voltage to a load; exhibit a fault; in response to the fault corresponding to a first category, transmit a first code voltage in a current sense (cs) signal; in response to the fault corresponding to a second category, transmit a reference voltage in the cs signal; receive, after transmission of the reference voltage, a tristate voltage in the pwm signal; and transmit, after receiving the tristate voltage, a second code voltage in the cs signal based on a type of the fault and the second category.
Inventor(s): Gregory North of Austin TX (US) for texas instruments incorporated, Sudhakar Surendran of Bangalore (IN) for texas instruments incorporated, Venkatraman Ramakrishnan of Bangalore (IN) for texas instruments incorporated
IPC Code(s): G06F1/06, G06F1/08
CPC Code(s): G06F1/06
Abstract: embodiments disclosed herein relate to managing clock signals across clock domains. in one implementation, a system is configured to derive a base clock signal from a first clock trigger signal produced by a first subsystem in a first clock domain of the clocking system. the system is further configured to generate a second clock trigger signal based on the base clock signal and a main clock of a second subsystem in a second clock domain of the clocking system. the system is also configured to supply the second clock trigger signal to a second peripheral in the second clock domain.
Inventor(s): ALAN DAVIS of Sugar Land TX (US) for texas instruments incorporated, VENKATESH NATARAJAN of Bangalore (IN) for texas instruments incorporated, ALEXANDER TESSAROLO of Lindfield (AU) for texas instruments incorporated
IPC Code(s): G06F9/38, G06F7/02
CPC Code(s): G06F9/3869
Abstract: a processor with instruction storage configured to store processor instructions, data storage configured to store processor data representing an array, the array including plural data elements, a controller, and an instruction pipeline. the instruction pipeline includes: a load stage circuit configured to load an array element from the data storage, a compare stage circuit configured to compare the array element to a reference value, a store stage circuit configured to store a set of results that includes a result of the comparison of the array element to the reference value, and a loop hit detect stage circuit configured to determine whether any of the set of results is associated with a hit on the reference value.
20240311235. HANDLING NON-CORRECTABLE ERRORS_simplified_abstract_(texas instruments incorporated)
Inventor(s): David Matthew THOMPSON of Dallas TX (US) for texas instruments incorporated, Abhijeet Ashok CHACHAD of Plano TX (US) for texas instruments incorporated
IPC Code(s): G06F11/10, G06F9/30, G06F9/38, G06F9/448, G06F9/46, G06F9/48, G06F9/52, G06F12/0811, G06F12/0815, G06F12/0879, G06F12/0888, G06F12/0895, G06F12/128, G06F13/16, H03M13/15
CPC Code(s): G06F11/106
Abstract: an example device includes a first memory that store a first set of data; a second memory that stores a second set of data that includes a stored error correcting code (ecc) value; and a controller coupled to the first memory and to the second memory. the controller operates to receive a transaction directed to the first set of data, and based on the transaction perform the following operations: retrieve the second set of data from the second memory; calculate a current ecc value based on the second set of data as retrieved from the second memory; compare the stored ecc value to the current ecc value to determine whether the second set of data includes an error; determine whether the error is correctable; and determine not to access the first memory to perform the transaction based on a determination that the second set of data includes the non-correctable error.
Inventor(s): Timothy David Anderson of University Park TX (US) for texas instruments incorporated, Mujibur Rahman of Plano TX (US) for texas instruments incorporated
IPC Code(s): G06F12/1045, G06F7/24, G06F7/487, G06F7/499, G06F7/53, G06F7/57, G06F9/30, G06F9/32, G06F9/345, G06F9/38, G06F9/48, G06F11/00, G06F11/10, G06F12/0862, G06F12/0875, G06F12/0897, G06F12/1009, G06F15/78, G06F17/16, H03H17/06
CPC Code(s): G06F12/1045
Abstract: various configurations of processors are provided. in a configuration, the processor comprises first and second multiplication units. the first multiplication unit includes first multiply circuitry including a first set of outputs; and first multiplexing logic coupled to the first set of outputs and configured to generate a first partial sum and a first partial carry. the second multiplication unit includes second multiply circuitry including a second set of outputs; and second multiplexing logic coupled to the second set of outputs and configured to generate a second partial sum and a first partial carry.
Inventor(s): Jose Franco A. Alicante of Baguio City (PH) for texas instruments incorporated, Roderick S. Balares of Baguio City (PH) for texas instruments incorporated, Christopher Abenes of Baguio City (PH) for texas instruments incorporated, Jeniffer Otero Aspuria of Baguio City (PH) for texas instruments incorporated
IPC Code(s): H01L21/304, H01L21/56, H01L21/683, H01L23/00
CPC Code(s): H01L21/304
Abstract: backgrinding a semiconductor wafer includes planarizing backgrind tape without requiring cutting the tape. a semiconductor substrate is provided with an active top surface and a back surface. the active top surface includes a plurality of bumps that connect to devices formed in or on the substrate. a backgrind tape is applied over the top surface of the substrate. the backgrind tape covers the bumps and extends to a periphery of the top surface. the top surface of the substrate is placed so that the backgrind tape is positioned on a chuck table of a backgrind apparatus. pressure is applied to the back surface of the substrate forcing the backgrind tape against the chuck table. the pressure is removed after a predetermined interval. backgrinding is performed on the back surface of the substrate to reach a target substrate thickness.
Inventor(s): Benjamin Stassen Cook of Addison TX (US) for texas instruments incorporated, Archana Venugopal of Dallas TX (US) for texas instruments incorporated, Luigi Colombo of Dallas TX (US) for texas instruments incorporated, Robert Reid Doering of Garland TX (US) for texas instruments incorporated
IPC Code(s): H01L23/367, H01L21/3205, H01L21/324, H01L21/74, H01L21/768, H01L23/373, H01L23/48, H01L23/522, H01L23/528, H01L23/532, H01L27/02
CPC Code(s): H01L23/367
Abstract: an integrated circuit includes a semiconductor substrate. the integrated circuit also includes a trench in the semiconductor substrate, the trench including a layer of a nanoparticle material. the integrated circuit further includes an interconnect region above the trench.
Inventor(s): Yanbiao Pan of Plano TX (US) for texas instruments incorporated, Robert Martin Higgins of Plano TX (US) for texas instruments incorporated, Bhaskar Srinivasan of Allen TX (US) for texas instruments incorporated, Pushpa Mahalingam of Richardson TX (US) for texas instruments incorporated
IPC Code(s): H01L27/06, H01L21/285
CPC Code(s): H01L27/0629
Abstract: apparatus, and their methods of manufacture, that include an insulating feature above a substrate and a resistor formed on the insulating feature. forming the resistor includes depositing polysilicon and doping the polysilicon (e.g., in-situ) with a carbon dopant and/or an oxygen dopant.
Inventor(s): Juan HERBSOMMER of Allen TX (US) for texas instruments incorporated, Hassan ALI of Murphy TX (US) for texas instruments incorporated, Claudia VASANELLI of Munich (DE) for texas instruments incorporated
IPC Code(s): H01P3/12, H01Q9/04, H01Q21/06
CPC Code(s): H01P3/122
Abstract: in one example, an apparatus includes a substrate, an antenna on the substrate, a sealed container enclosing a dipolar gas, a waveguide, and a stub. the waveguide is communicatively coupled between the antenna and the sealed container. the waveguide is separated from the substrate by a gap. the stub is adjacent to the waveguide and extends away from the gap.
Inventor(s): Harshpreet Singh Phull Bakshi of Dallas TX (US) for texas instruments incorporated, Rajen Manicon Murugan of Dallas TX (US) for texas instruments incorporated, Sylvester Ankamah-Kusi of Dallas TX (US) for texas instruments incorporated
IPC Code(s): H01Q9/04, H01Q1/22, H01Q1/38, H01Q1/42
CPC Code(s): H01Q9/0407
Abstract: an electronic device includes a multilevel package substrate, a semiconductor die, and a package structure, the multilevel package substrate has first, second, and third levels including respective dielectric layers and conductive features, the first level including a first trace layer with an antenna and a first via layer with a portion of a ground wall laterally spaced outward from and surrounding the antenna, and the second level including a second trace layer having a ground plane connected to the ground wall, the semiconductor die attached to the first level of the multilevel package substrate, and the package structure including a molding compound enclosing the semiconductor die and extending on a side of the antenna, where the package structure mold compound maters and thickness can be tuned for improved performance.
Inventor(s): Henry L. Edwards of Garland TX (US) for texas instruments incorporated, Wei Da of Manchester NH (US) for texas instruments incorporated, Stephen Brink of Manchester NH (US) for texas instruments incorporated, Joseph Maurice Khayat of Bedford NH (US) for texas instruments incorporated
IPC Code(s): H02M3/158, H02M1/08, H02M1/34
CPC Code(s): H02M3/158
Abstract: a switching regulator includes a low-side switching transistor, a snubber transistor, a first pull-down transistor, and a second pull-down transistor. the low-side switching transistor includes a first current terminal and a second current terminal. the first current terminal is coupled to a switching node. the second current terminal is coupled to a ground terminal. the snubber transistor includes a first current terminal, a second current terminal, and a control terminal. the first current terminal is coupled to the switching node. the second current terminal is coupled to the ground terminal. the first pull-down transistor is coupled between the control terminal of the snubber transistor and the ground terminal. the second pull-down transistor is coupled between the control terminal of the snubber transistor and the ground terminal.
Inventor(s): Saad PERVAIZ of Tyler TX (US) for texas instruments incorporated, Johan STRYDOM of Saratoga CA (US) for texas instruments incorporated, Michael LUEDERS of Freising (DE) for texas instruments incorporated, Laszlo BALOGH of Merrimack NH (US) for texas instruments incorporated
IPC Code(s): H02M3/335, H02M1/08
CPC Code(s): H02M3/33507
Abstract: an apparatus includes: a first transistor coupled between a primary-side terminal and a bias terminal, the first transistor having a first control terminal; a second transistor coupled between the bias terminal and a ground terminal, the second transistor having a second control terminal; and a control circuit having a control input, a reference input, and first and second control outputs, the control input coupled to the bias terminal, the first control output coupled to the first control terminal, the second control output coupled to the second control terminal, and the control circuit configured to provide first and second control signals having a same switching frequency at the respective first and second control outputs responsive to a first voltage at the control input and a second voltage at the reference input.
Inventor(s): Laszlo Balogh of Merrimack NH (US) for texas instruments incorporated, Michael Lueders of Freising (DE) for texas instruments incorporated, Stefan Herzer of Marzling (DE) for texas instruments incorporated, Maik Peter Kaufmann of Freising (DE) for texas instruments incorporated
IPC Code(s): H02M3/335, H02M1/00, H02M1/36
CPC Code(s): H02M3/33576
Abstract: a self-biasing circuit for power converters is disclosed. in an example, an apparatus includes a first transistor coupled between an inductor terminal and a ground terminal, and a second transistor coupled between the inductor terminal and a bias terminal. the first transistor has a first control terminal, and the second transistor has a second control terminal. in an example, the first and second transistors are configured to split a current at the inductor terminal. the apparatus further includes a controller having first and second control outputs, where the first control output is coupled to the first control terminal, the second control output is coupled to the second control terminal.
Inventor(s): Gregory North of Austin TX (US) for texas instruments incorporated, Sudhakar Surendran of Bangalore (IN) for texas instruments incorporated, Venkatraman Ramakrishnan of Bangalore (IN) for texas instruments incorporated
IPC Code(s): H03K5/00, H03K3/037, H03K5/133, H03K21/10
CPC Code(s): H03K5/00006
Abstract: embodiments disclosed herein relate to the management of a multi-trim oscillator to provide synchronization across multiple frequencies derived from the multi-trim oscillator without causing spurious pulses of clock output. in one example, a system provides a first clock signal via an oscillator and a second clock signal based on the first clock signal and a divider. the system further receives a first signal that indicates a change in a frequency of the first clock signal from a first frequency to a second frequency. in response to the first signal, the system determines an edge of the second clock signal and provides, at a time based on the edge of the second clock signal, a second signal to the oscillator to cause the change to the second frequency.
20240313751. ECG INTERFERENCE SUPPRESSION_simplified_abstract_(texas instruments incorporated)
Inventor(s): Sachin AITHAL of Bangalore (IN) for texas instruments incorporated, Anand H UDUPA of Bangalore (IN) for texas instruments incorporated, Raja Reddy PATUKURI of Bengaluru (IN) for texas instruments incorporated, Sandeep OSWAL of Bangalore (IN) for texas instruments incorporated, Aatish CHANDAK of Bangalore (IN) for texas instruments incorporated, Vignesh SUBRAMANYA of Bangalore (IN) for texas instruments incorporated, Aravind MIRIYALA of Bangalore (IN) for texas instruments incorporated
IPC Code(s): H03K5/1252, A61B5/00, A61B5/349, H03M1/12
CPC Code(s): H03K5/1252
Abstract: a circuit includes an interference frequency tracking circuit, a pli synthesizer circuit, and a summing circuit. the interference frequency tracking circuit is configured to track a frequency of an interference signal derived from a target signal, and provide a frequency selection value representing the frequency of the interference signal. the pli synthesizer circuit is configured to generate, based on the frequency selection value, a correction signal at the frequency of the interference signal, adjust a phase of the correction signal to match a phase of the interference signal in the target signal, and adjust an amplitude of the correction signal to match an amplitude of the interference signal in the target signal. the summing circuit is configured to subtract the correction signal from the target signal.
Inventor(s): Sri Navaneethakrishnan Easwaran of Plano TX (US) for texas instruments incorporated, Angelo Pereira of Allen TX (US) for texas instruments incorporated, Yueming Sun of SHANGHAI (CN) for texas instruments incorporated, Kae Wong of ALLEN TX (US) for texas instruments incorporated, Ahmed E Hashim of GILBERT AZ (US) for texas instruments incorporated, Artur Lewinski of Dallas TX (US) for texas instruments incorporated
IPC Code(s): H03K17/687, H03K17/10, H03K17/567
CPC Code(s): H03K17/687
Abstract: described embodiments include a voltage converter power circuit having a high-voltage rated first transistor with a first current terminal coupled to an input voltage terminal, and a second current terminal. a second transistor, a low-voltage rated transistor, has a second control terminal, a third current terminal coupled to the second current terminal, and a fourth current terminal coupled to a switching terminal. a third transistor, a high-voltage rated transistor, has a fifth current terminal coupled to the switching terminal, a sixth current terminal, and a third control terminal. a fourth transistor, a low-voltage rated transistor, is coupled between the sixth current terminal and a ground terminal. a bleeder circuit is coupled between the seventh and eighth current terminals and is configured to prevent a voltage across the fourth transistor from exceeding a breakdown voltage.
Inventor(s): Bhavesh G. Bhakta of Richardson TX (US) for texas instruments incorporated, Venkateswara Reddy Pothireddy of McKinney TX (US) for texas instruments incorporated, Abhijit Kumar Das of Plano TX (US) for texas instruments incorporated
IPC Code(s): H03L7/081, H03L7/085
CPC Code(s): H03L7/0818
Abstract: an example system includes a controller having a first controller terminal, a second controller terminal, and a third controller terminal and digitally locked loop (dll) circuitry having a first dll terminal and a second dll terminal, the first dll terminal coupled to the first controller terminal. the system also includes first retimer circuitry having a first retimer terminal, and a second retimer terminal, and a third retimer terminal, the first retimer terminal coupled to the second dll terminal and the second retimer terminal coupled to the second controller terminal and second retimer circuitry having a fourth retimer terminal, a fifth retimer terminal, and a sixth retimer terminal, the fourth retimer terminal coupled to the second dll terminal and the fifth retimer terminal coupled to the third controller terminal.
Inventor(s): Deepak Kumar MEHER of Bengaluru (IN) for texas instruments incorporated, Gautam NANDI of Bengaluru (IN) for texas instruments incorporated, Tarun PUROHIT of Bengaluru (IN) for texas instruments incorporated
IPC Code(s): H03M1/10
CPC Code(s): H03M1/1023
Abstract: a circuit includes a digital-to-analog converter and a gain stage. the gain stage includes: an operational amplifier; a variable gain network; and a leakage current control circuit. a first input of the operational amplifier is coupled to an input of the gain stage. an output of the operational amplifier is coupled to an output of the gain stage. a first terminal of the variable gain network is coupled to the second input of the operational amplifier. a second terminal of the variable gain network is coupled to the output of the operational amplifier. a first terminal of the leakage current control circuit is coupled to the output of the operational amplifier. a second terminal of the leakage current control circuit coupled to a third terminal of the variable gain network.
Inventor(s): Rohit CHATTERJEE of Bengaluru (IN) for texas instruments incorporated, Debapriya SAHU of Bengaluru (IN) for texas instruments incorporated
IPC Code(s): H04B1/00, H04B1/04
CPC Code(s): H04B1/0064
Abstract: a transmitter comprises an antenna array demultiplexor having a first input for an output signal, a second input for a control signal, a first output coupled to a first output pin, and a second output coupled to a second output pin. the antenna array demultiplexor provides the output signal to the first or second output based on the control signal. the first and second output pins are coupled to first and second antennae, respectively. in some implementations, the transmitter includes a transformer and a capacitor coupled in parallel between the first and second output pins, and the antenna array demultiplexor comprises a first switch coupled between the first output pin and a first ground pin, and a second switch coupled between the second output pin and a second ground pin. the first switch receives a second control signal, and the second switch receives an inverse of the second control signal.
Inventor(s): Ariton E. Xhafa of Plano TX (US) for texas instruments incorporated, Xiaolin Lu of Allen TX (US) for texas instruments incorporated, Janwei Zhou of Plano TX (US) for texas instruments incorporated, Il Han Kim of Allen TX (US) for texas instruments incorporated
IPC Code(s): H04B1/7156, H04B1/713, H04L9/06, H04L9/40, H04W12/037, H04W12/0471
CPC Code(s): H04B1/7156
Abstract: a network includes a first wireless node that communicates over a wireless network connection. the first wireless node includes a first encryption engine that processes a first initialization data set and a current transmit sequence associated with a current communication to generate a next transmit sequence that is employed to communicate with a second wireless node that derives a next received sequence that corresponds to the next transmit sequence to process a subsequent communication.
Inventor(s): Peter Wongeun CHUNG of Frisco TX (US) for texas instruments incorporated, Alexander D’ABREU of Dallas TX (US) for texas instruments incorporated, Arvind KANDHALU of Plano TX (US) for texas instruments incorporated, Max WENNERFELDT of Norrköping (SE) for texas instruments incorporated
IPC Code(s): H04L69/18
CPC Code(s): H04L69/18
Abstract: a method includes assigning a priority to each of a plurality of protocol activities to produce stack priority information for each of a plurality of protocol stacks. the method further includes dynamically adjusting the priority of each of the plurality of protocol activities in the stack priority information based on a network maintenance activity and based on a rejection or an acceptance of the corresponding protocol activity by a dynamic multi-protocol manager (dmm). the method further includes providing the stack priority information to the dmm.
Inventor(s): Mangesh Devidas Sadafale of Bengaluru (IN) for texas instruments incorporated, Minhua Zhou of San Diego CA (US) for texas instruments incorporated
IPC Code(s): H04N19/86, H04N19/117, H04N19/157, H04N19/176, H04N19/436
CPC Code(s): H04N19/86
Abstract: deblocking filtering is provided in which an 8�8 filtering block covering eight sample vertical and horizontal boundary segments is divided into filtering sub-blocks that can be independently processed. to process the vertical boundary segment, the filtering block is divided into top and bottom 8�4 filtering sub-blocks, each covering a respective top and bottom half of the vertical boundary segment. to process the horizontal boundary segment, the filtering block is divided into left and right 4�8 filtering sub-blocks, each covering a respective left and right half of the horizontal boundary segment. the computation of the deviation d for a boundary segment in a filtering sub-block is performed using only samples from rows or columns in the filtering sub-block. consequently, the filter on/off decisions and the weak/strong filtering decisions of the deblocking filtering are performed using samples contained within individual filtering blocks, thus allowing full parallel processing of the filtering blocks.
Inventor(s): Yaron ALPERT of Hod Hasharon (IL) for texas instruments incorporated, Maxim ALTSHUL of Hod Hasharon (IL) for texas instruments incorporated, Maital HAHN of Petach-Tikva (IL) for texas instruments incorporated
IPC Code(s): H04W68/00, H04W4/23, H04W4/80
CPC Code(s): H04W68/005
Abstract: a bluetooth (bt) or bluetooth low energy (ble) controller includes: a physical (phy) layer; a baseband radio frequency (rf) layer; and a link layer (ll). the ll is configured to: obtain an incoming transmission awareness request regarding a later incoming transmission event; and perform incoming transmission operations to prepare for the later incoming transmission event responsive to the incoming transmission awareness request.
Texas Instruments Incorporated patent applications on September 19th, 2024
- Texas Instruments Incorporated
- G01R1/067
- CPC G01R1/06766
- Texas instruments incorporated
- G01R31/28
- G01R19/18
- G01R35/00
- H03F3/04
- CPC G01R31/2834
- G01R31/319
- G01R31/3167
- H03M1/06
- H03M1/10
- CPC G01R31/31922
- G01R31/40
- CPC G01R31/40
- G06F1/06
- G06F1/08
- CPC G06F1/06
- G06F9/38
- G06F7/02
- CPC G06F9/3869
- G06F11/10
- G06F9/30
- G06F9/448
- G06F9/46
- G06F9/48
- G06F9/52
- G06F12/0811
- G06F12/0815
- G06F12/0879
- G06F12/0888
- G06F12/0895
- G06F12/128
- G06F13/16
- H03M13/15
- CPC G06F11/106
- G06F12/1045
- G06F7/24
- G06F7/487
- G06F7/499
- G06F7/53
- G06F7/57
- G06F9/32
- G06F9/345
- G06F11/00
- G06F12/0862
- G06F12/0875
- G06F12/0897
- G06F12/1009
- G06F15/78
- G06F17/16
- H03H17/06
- CPC G06F12/1045
- H01L21/304
- H01L21/56
- H01L21/683
- H01L23/00
- CPC H01L21/304
- H01L23/367
- H01L21/3205
- H01L21/324
- H01L21/74
- H01L21/768
- H01L23/373
- H01L23/48
- H01L23/522
- H01L23/528
- H01L23/532
- H01L27/02
- CPC H01L23/367
- H01L27/06
- H01L21/285
- CPC H01L27/0629
- H01P3/12
- H01Q9/04
- H01Q21/06
- CPC H01P3/122
- H01Q1/22
- H01Q1/38
- H01Q1/42
- CPC H01Q9/0407
- H02M3/158
- H02M1/08
- H02M1/34
- CPC H02M3/158
- H02M3/335
- CPC H02M3/33507
- H02M1/00
- H02M1/36
- CPC H02M3/33576
- H03K5/00
- H03K3/037
- H03K5/133
- H03K21/10
- CPC H03K5/00006
- H03K5/1252
- A61B5/00
- A61B5/349
- H03M1/12
- CPC H03K5/1252
- H03K17/687
- H03K17/10
- H03K17/567
- CPC H03K17/687
- H03L7/081
- H03L7/085
- CPC H03L7/0818
- CPC H03M1/1023
- H04B1/00
- H04B1/04
- CPC H04B1/0064
- H04B1/7156
- H04B1/713
- H04L9/06
- H04L9/40
- H04W12/037
- H04W12/0471
- CPC H04B1/7156
- H04L69/18
- CPC H04L69/18
- H04N19/86
- H04N19/117
- H04N19/157
- H04N19/176
- H04N19/436
- CPC H04N19/86
- H04W68/00
- H04W4/23
- H04W4/80
- CPC H04W68/005
