Texas Instruments Incorporated patent applications on October 10th, 2024
Patent Applications by Texas Instruments Incorporated on October 10th, 2024
Texas Instruments Incorporated: 17 patent applications
Texas Instruments Incorporated has applied for patents in the areas of G01R31/28 (2), H03F3/45 (2), H03M1/66 (2), H03K17/687 (2), H01L23/00 (2) G01R31/2834 (1), H01L27/1203 (1), H04N19/167 (1), H03M1/0612 (1), H03K17/6871 (1)
With keywords such as: voltage, terminal, coupled, current, input, circuit, having, transistor, based, and power in patent application abstracts.
Patent Applications by Texas Instruments Incorporated
Inventor(s): Rajavelu Thinakaran of Bangalore (IN) for texas instruments incorporated
IPC Code(s): G01R31/28, H03K17/687
CPC Code(s): G01R31/2834
Abstract: in described examples, a system includes a resistor, a capacitor coupled to the resistor to form an rc circuit, and a charging circuit. the charging circuit is coupled to the resistor and to the capacitor. the charging circuit is configured to determine a voltage across the resistor, and to provide a current to the capacitor to increase a rate of charging or discharging of the capacitor. a magnitude and a polarity of the current are responsive to the voltage across the resistor. in some examples, the rc circuit is configured to compensate for a load capacitance of a parametric measurement unit, a source measurement unit, or a device power supply that is part of an automatic test equipment.
Inventor(s): Tanmay Neema of Bangalore (IN) for texas instruments incorporated, Kanak Das of Bangalore (IN) for texas instruments incorporated, Rajavelu Thinakaran of Bangalore (IN) for texas instruments incorporated, Gautam Nandi of Bangalore (IN) for texas instruments incorporated
IPC Code(s): G01R31/28, H03F3/45, H03M1/66
CPC Code(s): G01R31/2879
Abstract: the techniques and circuits, described herein, include solutions for error compensation in source measurement units (smus). an example smu is capable of both sourcing current to a device under test (dut) and measuring current through the dut. an smu may include a sensing resistor coupled in series with the dut. a voltage across the sensing resistor may be measured by a current sensing amplifier in order to determine the output current through the dut. in practice, the resistance of the sensing resistor may vary depending on manufacturing tolerances, etc. a gain of the current sensing amplifier may be calibrated in order to compensate for sensing resistor variance, which increases the accuracy with which current to the dut can be sourced and measured.
Inventor(s): Lee D. Whetsel of Parker TX (US) for texas instruments incorporated
IPC Code(s): G01R31/3183, G01R31/317, G01R31/3177, G01R31/3185, G06F11/273
CPC Code(s): G01R31/318335
Abstract: the disclosure describes novel methods and apparatuses for accessing test compression architectures (tca) in a device using either a parallel or serial access technique. the serial access technique may be controlled by a device tester or by a jtag controller. further the disclosure provides an approach to access the tca of a device when the device exists in a daisy-chain arrangement with other devices, such as in a customer's system. additional embodiments are also provided and described in the disclosure.
Inventor(s): Yicheng Zhou of Shanghai (CN) for texas instruments incorporated, Xiaodong Li of Shanghai (CN) for texas instruments incorporated, Yuhao Zhao of Shanghai (CN) for texas instruments incorporated
IPC Code(s): G01R31/367, G01R31/388
CPC Code(s): G01R31/367
Abstract: a method comprises recording a first voltage value of a voltage source, recording a second voltage value of the voltage source, and determining a first estimated residual state of charge value (soc) of the voltage source based on the first voltage value and the second voltage value. the method also comprises determining a factor based on one of the first voltage value and the second voltage value and calculating a residual state of charge value (soc) of the voltage source based on the first estimated residual state of charge value (soc) and based on the factor.
Inventor(s): Dimitar Trifonov of Vail AZ (US) for texas instruments incorporated, Chao-Hsiuan Tsay of Tucson AZ (US) for texas instruments incorporated, Chase Mackenzie Puglisi of Tucson AZ (US) for texas instruments incorporated, Arup Polley of Bangalore (IN) for texas instruments incorporated
IPC Code(s): G01R33/00, G01R33/07
CPC Code(s): G01R33/0035
Abstract: methods, apparatus, systems, and articles of manufacture are described corresponding to wide bandwidth hall sensing circuitry. an example circuit includes a first hall effect sensor configured to output a first voltage corresponding to a magnetic field; an amplifier to output an amplified voltage by amplifying the first voltage; a second hall effect sensor configured to output a second voltage corresponding to the magnetic field, the second hall effect sensor operating using a spinning technique to toggle a bias current between terminals of the second hall effect sensor, the spinning technique to remove a first offset corresponding to the second hall effect sensor; and offset reduction circuitry configured to: determine a second offset corresponding to the first hall effect sensor based on the first voltage and the second voltage; and generate an output based on the second offset, the amplifier to adjust the amplified voltage based on the output.
Inventor(s): Pramod Swami of Bangalore (IN) for texas instruments incorporated, Mihir Mody of Bangalore (IN) for texas instruments incorporated, Deepak Poddar of Bangalore (IN) for texas instruments incorporated
IPC Code(s): G06F9/50
CPC Code(s): G06F9/5038
Abstract: various examples disclosed herein relate to digital signal processing, and more particularly, to processing stages of multi-channel processing pipelines in batches according to an order. a method of such processing is provided and includes retrieving multi-channel data from a memory and processing the multi-channel data with a hardware accelerator implementing a multi-stage processing pipeline for each channel of a plurality of channels. the multi-stage processing pipelines can be arranged in a cyclically descending order based on a total number of stages of each multi-stage processing pipeline. processing the multi-channel data includes sequentially processing a plurality of batches each including one or more stages from different multi-stage processing pipelines adjacent to each other in the cyclically descending order. processing the plurality of batches may include processing corresponding ones of the stages in parallel.
Inventor(s): Sureshkumar Govindaraj of Irving TX (US) for texas instruments incorporated
IPC Code(s): G06F12/123, G06F12/06
CPC Code(s): G06F12/123
Abstract: a method is provided that includes searching tags in a tag group comprised in a tagged memory system for an available tag line during a clock cycle, wherein the tagged memory system includes a plurality of tag lines having respective tags and wherein the tags are divided into a plurality of non-overlapping tag groups, and searching tags in a next tag group of the plurality of tag groups for an available tag line during a next clock cycle when the searching in the tag group does not find an available tag line.
Inventor(s): YOU CHYE HOW of MELAKA (MY) for texas instruments incorporated, HUAY YANN TAY of MELAKA (MY) for texas instruments incorporated, WEI LI JULIEN MOK of MELAKA (MY) for texas instruments incorporated
IPC Code(s): H01L23/495, H01L21/48, H01L21/56, H01L23/00
CPC Code(s): H01L23/49541
Abstract: an electronic device that includes a leadframe having contact pads, where at least two adjacent contact pads of the contact pads are disconnected from each other via a slot. a die includes input/output pins, where the input/output pins are connected to respective contact pads of the contact pads on the leadframe. interconnects connect the input/output pins to the respective contact pads. a mold compound encapsulates the die and the interconnects.
Inventor(s): Ymarson Algamas Bangaga of Baguio City (PH) for texas instruments incorporated, Patricio V. Ancheta, JR. of Baguio City (PH) for texas instruments incorporated, Rachel F. Dulatre of Baguio City (PH) for texas instruments incorporated
IPC Code(s): H01L23/495, H01L21/56, H01L23/31
CPC Code(s): H01L23/49548
Abstract: an example apparatus includes: a leadframe having upset leads, the leads further including: an external portion with a board side surface in a first plane; an internal portion extending from the external portion and having an upper surface opposite the board side surface; an angled portion extending from the internal portion and forming an angle with the upper surface; and an elevated portion extending from the angled portion and having a device side surface lying in a second plane parallel to the first plane. a mold lock feature includes an indenture into the upper surface or the angle being either a normal angle or an acute angle formed between the upper surface and the angled portion. a semiconductor die is flip chip mounted to the elevated portion of the leads. mold compound covers the semiconductor die and is in contact with the mold lock feature of the leads.
20240339457. CONTAMINANT COLLECTION ON SOI_simplified_abstract_(texas instruments incorporated)
Inventor(s): Honglin Guo of Dallas TX (US) for texas instruments incorporated, Frank John Sweeney of Rockwall TX (US) for texas instruments incorporated
IPC Code(s): H01L27/12, H01L21/265, H01L23/00, H01L29/94, H01L33/64
CPC Code(s): H01L27/1203
Abstract: an integrated circuit includes an soi substrate having a semiconductor layer over a buried insulator layer. an electronic device has an nwell region in the semiconductor layer, a dielectric over the nwell region, and a polysilicon plate over the dielectric. a white space region adjacent the electronic device includes a first p-type region in the semiconductor layer and adjacent the surface. the p-type region has a first sheet resistance and the nwell region has a second sheet resistance that is greater than the first sheet resistance.
Inventor(s): Tawen MEI of Sunnyvale CA (US) for texas instruments incorporated
IPC Code(s): H02M1/00, H02M3/156
CPC Code(s): H02M1/0003
Abstract: in some examples, a switch-mode power supply circuit comprises a pulse generation circuit comprising an oscillator, the oscillator configured to generate first pulses using a fixed frequency regulation for a first load condition that exceeds a predefined threshold and configured to generate second pulses using a variable frequency regulation for a second load condition that does not exceed the predefined threshold. the circuit also includes a power converter coupled to the pulse generation circuit and configured to convert a first voltage to a regulated voltage using either one of the first or second pulses generated by the pulse generation circuit. the circuit further comprises an output filter coupled to the power converter and configured to produce a second voltage from the regulated voltage.
Inventor(s): Manish Bhardwaj of Sugarland TX (US) for texas instruments incorporated
IPC Code(s): H02M1/42, H02M7/217
CPC Code(s): H02M1/4208
Abstract: example power factor correction circuits to correct the power factor of power converters are disclosed. an example power factor correction controller circuit includes a phase locked loop phase angle determiner to determine a first phase angle of an input voltage of the power converter and further includes a compensating current determiner to determine, based on the phase angle, a compensating current to compensate for a capacitive current introduced by at least one filter capacitor of the power converter. the power factor correction controller circuit further includes a switch controller to cause a controlled current drawn by a power stage of the power converter to be adjusted by the compensating current to reduce a phase offset between the first phase angle of the input voltage and a second phase angle of the input current drawn at an input of the power converter.
Inventor(s): Dimitar Trifonov of Tucson AZ (US) for texas instruments incorporated, Chao-Hsiuan Tsay of Tucson AZ (US) for texas instruments incorporated, Chase Puglisi of Tucson AZ (US) for texas instruments incorporated
IPC Code(s): H03F3/45
CPC Code(s): H03F3/45381
Abstract: in some examples, an amplifier includes a pair of input differential transistors a pair of feedback transistors, a pair of current sources, a pair of gain setting resistors, and a tail current transistor. control terminals of the feedback transistors are respectively coupled to first terminals of the input differential transistors. the pair of current sources are respectively coupled to the control terminals of the feedback transistors and the first terminals of the input differential transistors. the pair of gain setting resistors have first terminals that are respectively coupled to the second terminals of the input differential transistors. the pair of gain setting resistors have second terminals that are coupled to one another. the tail current transistor has a first terminal coupled to the second terminals of the gain setting resistors and a second terminal coupled to a dc supply.
Inventor(s): Kelvin Le of Dallas TX (US) for texas instruments incorporated, Saleh Ahmad of Dallas TX (US) for texas instruments incorporated, Riccardo Ruffo of Munich (DE) for texas instruments incorporated
IPC Code(s): H03K17/687
CPC Code(s): H03K17/6871
Abstract: an example apparatus includes: a first transistor having a first terminal and a control terminal; a second transistor having a first terminal and a control terminal, the first terminal of the second transistor coupled to the first terminal of the first transistor, the control terminal of the second transistor coupled to the control terminal of the first transistor; a resistor having a first terminal and a second terminal, the first terminal of the resistor coupled to the first terminal of the first transistor and the first terminal of the second transistor, the second terminal of the resistor coupled to the control terminal of the first transistor and the control terminal of the second transistor; and a diode having a first terminal and a second terminal, the first terminal of the diode coupled to the control terminal of the first transistor and the control terminal of the second transistor.
Inventor(s): Brian Elies of Dallas TX (US) for texas instruments incorporated
IPC Code(s): H03M1/06, H03M1/66, H03M1/80, H03M3/00
CPC Code(s): H03M1/0612
Abstract: an example apparatus includes: resistor ladder circuitry including a plurality of intermediate voltage nodes; a first plurality of switches having inputs coupled to a plurality of intermediate voltage nodes and having outputs; first level decoder circuitry configured to: receive a set of input bits; and open or close ones of the first plurality of switches based on a first subset of the input bits; a second plurality of switches having inputs coupled to the outputs of the first plurality of switches and having outputs coupled to a common node; and second level decoder circuitry configured to: receive the set of input bits; and open or close ones of the second plurality of switches based on a second subset of the input bits, the first and the second subsets sharing one of the input bits, wherein the output voltage is to be coupled to the common node.
Inventor(s): Yashwant Dutt of Bangalore (IN) for texas instruments incorporated, Kumar Desappan of Bangalore (IN) for texas instruments incorporated, Piyali Goswami of Bangalore (IN) for texas instruments incorporated
IPC Code(s): H04N19/167, H04N19/103, H04N19/124, H04N19/157, H04N19/176
CPC Code(s): H04N19/167
Abstract: several methods and systems for masking multimedia data are disclosed. in an embodiment, a method for masking includes performing a prediction for at least one multimedia data block based on a prediction mode of a plurality of prediction modes. the at least one multimedia data block is associated with a region of interest (roi). a residual multimedia data associated with the at least one multimedia data block is generated based on the prediction. a quantization of the residual multimedia data is performed based on a quantization parameter (qp) value. the qp value is variable such that varying the qp value controls a degree of masking of the roi.
Inventor(s): Minhua Zhou of San Diego CA (US) for texas instruments incorporated
IPC Code(s): H04N19/463, H04N19/109, H04N19/176, H04N19/50, H04N19/625
CPC Code(s): H04N19/463
Abstract: methods are provided for inter-prediction candidate index coding independent of the construction of the corresponding inter-prediction candidate list, i.e., a merging candidate list or an advanced motion vector predictor list. a maximum allowed number of inter-prediction candidates for an inter-prediction candidate list is used for encoding the inter-prediction candidate index in an encoded bit stream. the maximum allowed number may be pre-determined or may be selected by the encoder and encoded in the bit stream. a decoder may then decode the index using the maximum allowed number of inter-prediction candidates independent of the construction of the corresponding inter-prediction candidate list.
Texas Instruments Incorporated patent applications on October 10th, 2024
- Texas Instruments Incorporated
- G01R31/28
- H03K17/687
- CPC G01R31/2834
- Texas instruments incorporated
- H03F3/45
- H03M1/66
- CPC G01R31/2879
- G01R31/3183
- G01R31/317
- G01R31/3177
- G01R31/3185
- G06F11/273
- CPC G01R31/318335
- G01R31/367
- G01R31/388
- CPC G01R31/367
- G01R33/00
- G01R33/07
- CPC G01R33/0035
- G06F9/50
- CPC G06F9/5038
- G06F12/123
- G06F12/06
- CPC G06F12/123
- H01L23/495
- H01L21/48
- H01L21/56
- H01L23/00
- CPC H01L23/49541
- H01L23/31
- CPC H01L23/49548
- H01L27/12
- H01L21/265
- H01L29/94
- H01L33/64
- CPC H01L27/1203
- H02M1/00
- H02M3/156
- CPC H02M1/0003
- H02M1/42
- H02M7/217
- CPC H02M1/4208
- CPC H03F3/45381
- CPC H03K17/6871
- H03M1/06
- H03M1/80
- H03M3/00
- CPC H03M1/0612
- H04N19/167
- H04N19/103
- H04N19/124
- H04N19/157
- H04N19/176
- CPC H04N19/167
- H04N19/463
- H04N19/109
- H04N19/50
- H04N19/625
- CPC H04N19/463
