Texas Instruments Incorporated patent applications on February 29th, 2024
Patent Applications by Texas Instruments Incorporated on February 29th, 2024
Texas Instruments Incorporated: 43 patent applications
Texas Instruments Incorporated has applied for patents in the areas of H01L23/498 (4), H01L23/49838 (4), G01R31/371 (4), H04W40/32 (4), H02M1/00 (3)
With keywords such as: coupled, output, input, circuit, terminal, device, signal, current, voltage, and configured in patent application abstracts.
See the following report for Texas Instruments Incorporated patent applications published on February 29th, 2024:
Texas Instruments Incorporated patent applications on February 29th, 2024
Patent Applications by Texas Instruments Incorporated
Inventor(s): John Wesley Hamlin of Dallas TX (US) for texas instruments incorporated, Kathleen Rose Ferreira of Dallas TX (US) for texas instruments incorporated, Sean C. O'Brien of Dallas TX (US) for texas instruments incorporated, Jose A. Martinez of Murphy TX (US) for texas instruments incorporated
IPC Code(s): B81C1/00, B81B3/00, G02B26/08
Abstract: example methods, systems, and apparatus described herein provide a minimally invasive technique of controlling shape and stress in a mems device. an example method includes depositing a layer of material continuously across a semiconductor wafer, exposing the layer of material to oxygen plasma to increase a relative amount of oxygen within the layer of material; and etching the layer of material after exposing the layer of material to the oxygen plasma.
Inventor(s): Santhosh Kumar Srinivasan of BENGALURU (IN) for texas instruments incorporated, Robert A. Neidorff of BEDFORD NH (US) for texas instruments incorporated, Ramakrishna Ankamreddi of BANGALORE (IN) for texas instruments incorporated, Sravya Kanneganti of Dallas TX (US) for texas instruments incorporated, Padmanabh S. Prabhu of Bangalore (IN) for texas instruments incorporated
IPC Code(s): G01K7/01
Abstract: described embodiments include a circuit for temperature sensing having a first current source coupled to a diode input terminal. the first current source provides a first current at a first current output. a second current source provides a second current at a second current output. the second current is larger than the first current. a first switch is coupled between the second current source output and the diode input terminal. a capacitor is coupled between the diode input terminal and a temperature output terminal. a second switch is coupled between the temperature output terminal and a ground terminal. the temperature output terminal provides a temperature signal having a voltage that is proportional to a temperature of a component.
20240069073.MULTI-LEVEL VOLTAGE DETECTOR_simplified_abstract_(texas instruments incorporated)
Inventor(s): Keliu Shu of Frisco TX (US) for texas instruments incorporated
IPC Code(s): G01R19/00, H02M1/00
Abstract: in one example, a method comprises: receiving a voltage from a power converter, and generating a comparison result representing a comparison between the voltage and a voltage threshold. the method further comprises providing one of a first current reference or a second current reference to the power converter responsive to the comparison result, in which the first and second current references represent different current levels.
Inventor(s): Jyothsna KUNDURU of Plano TX (US) for texas instruments incorporated, Ariton XHAFA of Plano TX (US) for texas instruments incorporated, Minghua FU of Plano TX (US) for texas instruments incorporated, Jonathan NAFZIGER of Dallas TX (US) for texas instruments incorporated
IPC Code(s): G01R31/371, G01R31/396, H01M10/42, H04W72/04
Abstract: a system includes a first plurality of secondary devices, each secondary device of the first plurality of secondary devices including a first wireless transmitter and a battery monitor integrated circuit (ic). the battery monitor ic is configured to obtain battery data from at least one battery cell, and the first wireless transmitter is configured to wirelessly transmit the battery data. a first primary device has a second wireless transmitter wirelessly coupled to the first wireless transmitters of the first plurality of secondary devices via a first wireless network. a second primary device has a second wireless transmitter. the second primary device is configured to detect a fault with the first primary device and, in response detection of the fault, to establish a second wireless network with the first plurality of secondary devices.
Inventor(s): Ariton E. XHAFA of Plano TX (US) for texas instruments incorporated, Tariq Ihab MUHANNA of Garland TX (US) for texas instruments incorporated, Mathew GIARAMITA of New York NY (US) for texas instruments incorporated, Naveen Kumar KALA of Austin TX (US) for texas instruments incorporated
IPC Code(s): G01R31/371, G01R31/382, H01M10/42
Abstract: in an example, a wireless battery management system includes one or more sets of battery cells. the wireless battery management system includes a primary node configured to broadcast a downlink packet in a first superframe. the wireless battery management system also includes a first secondary node coupled to a first set of battery cells. the first secondary node is configured to receive the downlink packet and transmit a first uplink packet to the primary node during the first superframe. the wireless battery management system includes a second secondary node coupled to a second set of battery cells. the second secondary node is configured to receive the first uplink packet from the first secondary node in the first superframe. the second secondary node is also configured to transmit a second uplink packet to the primary node during a second superframe.
20240069186.ON-FIELD PHASE CALIBRATION_simplified_abstract_(texas instruments incorporated)
Inventor(s): Sandeep Rao of Bangalore (IN) for texas instruments incorporated, Karthik Subburaj of Bangalore (IN) for texas instruments incorporated
IPC Code(s): G01S13/58, G01S7/40
Abstract: a radar transceiver includes a phase shifter that is controlled to apply an induced phase shift in a first subset of chirp signals of a frame of chirp signals, which also includes a second subset of chirp signals in which no phase shift is applied. other circuitry generates digital signals based on received reflected signals, which are based on transmitted signals. processing circuitry performs a fast fourier transform (fft) on a first subset of digital signals, corresponding to the first subset of chirp signals, to generate a first range-doppler array, and performs a fft on the second subset of digital signals, corresponding to the second subset of chirp signals, to generate a second range-doppler array; identifies peaks in the first and second range-doppler arrays to detect an object; and compares a phases of peaks at corresponding positions in the first and second range-doppler arrays to determine a measured phase shift between the two peaks.
Inventor(s): David P. FOLEY of Sugar Land TX (US) for texas instruments incorporated, Alexander TESSAROLO of Lindfield (AU) for texas instruments incorporated, Alan L. DAVIS of Sugar Land TX (US) for texas instruments incorporated
IPC Code(s): G06F9/30, G06F21/54
Abstract: in an example, a system includes a processor, where the processor includes a plurality of processor registers, and where the processor is configured to execute a first instruction in a first execution context. the processor is also configured to receive a preserve instruction that indicates at least one processor register among the plurality of processor registers. the processor is configured to, responsive to the preserve instruction, preserve parameters in the at least one processor register and clear other processor registers in the plurality of processor registers in the first execution context. the processor is also configured to execute a second instruction in a second execution context.
Inventor(s): Aravind Lakshminarayanan of Frisco TX (US) for texas instruments incorporated, Jeffrey Kempf of Dallas TX (US) for texas instruments incorporated, Paul Rancuret of McKinney TX (US) for texas instruments incorporated
IPC Code(s): G09G3/34, G09G3/00
Abstract: an example apparatus comprising: a controller configured to: access a content brightness map; determine an amplitude of a light emitting diode (led) current based on the content brightness map, a target brightness, or a target color temperature; determine a pulse width modulation (pwm) sequence based on the content brightness map, the target brightness, or the target color temperature; determine an led pwm signal based on the content brightness map, the target brightness, the target color temperature, or the amplitude of the led current; transmit a signal indicating the led current to an led; transmit the pwm sequence to a spatial light modulator (slm); and transmit the led pwm signal to the led.
Inventor(s): Likhita Chandrashekara of Bangalore (IN) for texas instruments incorporated, Yash Didhe of DOMBIVLI (IN) for texas instruments incorporated, Rajat Chauhan of Bangalore (IN) for texas instruments incorporated, Devraj Rajagopal of Bangalore (IN) for texas instruments incorporated
IPC Code(s): G11C17/18, G11C17/16, H01L23/525, H10B20/25
Abstract: one example includes an integrated circuit with a sense amplifier that includes a first inverter having a first positive power terminal, a first input and a first output; and a second inverter having a second positive power terminal, a second input connected to the first output and a second output connected to the first input. the integrated circuit also includes a reference resistor connected between a positive voltage rail and the second positive power terminal. a fuse is connected between the positive voltage rail and the first positive power terminal.
20240071561.SRAM REPAIR SYSTEM AND METHOD_simplified_abstract_(texas instruments incorporated)
Inventor(s): Robin O. Hoel of Olso (NO) for texas instruments incorporated, Praveen Kumar Narayanan of Bangalore (IN) for texas instruments incorporated, Ruchi Shankar of Bengaluru (IN) for texas instruments incorporated
IPC Code(s): G11C29/00, G11C11/418
Abstract: an electronic system includes a repair mmr coupled with a first sram module within a plurality of sram modules coupled with each other in a daisy-chain configuration on a repair interface, and coupled with a last sram module within the plurality of sram modules via the repair interface. the electronic system also includes storage memory configured to store repair data for the plurality of sram modules and repair instructions, and processing circuitry. the processing circuitry is configured to, during boot up of the electronic system, read repair data for one or more of the plurality of sram modules from the storage memory, create serialized repair data for one or more the plurality of sram modules based on the repair instructions and the repair data, and to sequentially transmit the serialized repair data to the mmr.
20240071694.MEMS SWITCH_simplified_abstract_(texas instruments incorporated)
Inventor(s): Gokhan Ariturk of Norman OK (US) for texas instruments incorporated, Adam Fruehling of Garland TX (US) for texas instruments incorporated
IPC Code(s): H01H1/00, H01H59/00, H01P1/12
Abstract: a microelectromechanical system (mems) switch implemented with a coplanar waveguide. the mems switch includes an input terminal, an output terminal. the mems switch includes a beam extending between the input terminal and the output terminal. the beam includes a first edge and a second edge coupled to a gate of the mems switch. the beam includes a third edge proximate the input terminal. the first edge includes a first set of finger contacts proximate a first corner of the beam and a second set of finger contacts proximate a second corner of the beam. the beam includes a fourth edge proximate the output terminal, the fourth edge opposing the third edge. the mems switch has a first anchor coupled to the input terminal. the first anchor includes a first segment extending from a region proximate the input terminal to a region overlying the first set of finger contacts.
Inventor(s): JOSE DANIEL TORRES of ANGELES CITY (PH) for texas instruments incorporated, KATLEEN FAJARDO TIMBOL of SICHUAN (CN) for texas instruments incorporated
IPC Code(s): H01L21/027, H01L21/48, H01L23/498
Abstract: an electronic device includes a substrate having electrical circuits and/or electronic devices disposed thereon. metal traces are formed on the substrate and include feet on each side of the metal traces that flare outward in opposite directions from each other where the metal traces overlie the substrate. a dielectric layer is formed on the substrate and a portion of the metal traces, and an interconnect is disposed on the metal traces.
Inventor(s): Michael Todd Wyant of DALLAS TX (US) for texas instruments incorporated
IPC Code(s): H01L21/784, H01L21/02, H01L21/3065, H01L23/50
Abstract: methods of separating semiconductor dies are described. the method can separate individual semiconductor dies from a semiconductor wafer without using a blade. the methods include a plasma etch process utilizing metal structures formed on a back side of the wafer as masks to remove a portion of the semiconductor wafer from the back side. the portion removed by the plasma etch process corresponds to the scribe lines between the semiconductor dies. the plasma etch process terminates at a dielectric layer formed on a front side of the wafer. the dielectric layer may be severed to complete the separation process. moreover, an ultrasonic water jet process may be utilized to remove burrs of the dielectric layer that has been severed.
Inventor(s): Bin Liu of Shenyang (CN) for texas instruments incorporated, Lin Lin of Chengdu (CN) for texas instruments incorporated, Yu Chen Li of Chengdu (CN) for texas instruments incorporated, Si Si Xie of Chendgu (CN) for texas instruments incorporated, Zhi Yun Liu of Chengdu (CN) for texas instruments incorporated, Bo Jiang of Chengdu (CN) for texas instruments incorporated
IPC Code(s): H01L21/66
Abstract: a wafer metrology system having a continuous dynamic sampling scheme configured to optimize a sampling rate for avi of process wafers in an ic fabrication flow based on acceptable quality levels. for a stable process, the process wafers may be sampled at a lower rate without negatively affecting quality control.
Inventor(s): Naweed Anjum of Murphy TX (US) for texas instruments incorporated, Michael Gerald Amaro of Naperville IL (US) for texas instruments incorporated, Makarand Ramkrishna Kulkarni of Dallas TX (US) for texas instruments incorporated
IPC Code(s): H01L23/498, H01L23/00
Abstract: a lead for a surface mount package for a semiconductor device, and the surface mount package employing the same. in one example, the lead includes a central segment with a first side and a second side, a first extension from a portion of the first side, and a second extension from a portion of the second side. the lead also includes a recess extending through a portion of the central segment, the first extension and the second extension.
Inventor(s): Kwang-Soo KIM of Sunnyvale CA (US) for texas instruments incorporated, Vivek ARORA of San Jose CA (US) for texas instruments incorporated, Woochan KIM of San Jose CA (US) for texas instruments incorporated
IPC Code(s): H01L23/498, H01L21/48, H01L21/56, H01L23/00, H01L23/31, H01L25/065
Abstract: in examples, a method of manufacturing a semiconductor package comprises providing a lead frame having multiple conductive pins coupled thereto; positioning the lead frame within a mold chase and applying a strip of mold compound to the multiple conductive pins along a length of the lead frame; trimming connections between the lead frame and the multiple conductive pins; bending the multiple conductive pins; trimming the strip of mold compound to singulate the multiple conductive pins from each other and from the lead frame to form singulated conductive pins; coupling a singulated conductive pin from among the singulated conductive pins to a substrate such that a portion of the strip of mold compound coupled to the singulated conductive pin is in contact with the substrate and such that a segment of the singulated conductive pin extends vertically in a plane that is orthogonal to the substrate; coupling a semiconductor die to the substrate; and covering the substrate, the semiconductor die, the portion of the strip of mold compound, and part of the singulated conductive pin with a second mold compound, such that a portion of the segment of the singulated conductive pin extends beyond a top surface of the second mold compound.
Inventor(s): Harshpreet Singh Phull BAKSHI of Dallas TX (US) for texas instruments incorporated, Sylvester ANKAMAH-KUSI of Dallas TX (US) for texas instruments incorporated, Siraj AKHTAR of Dallas TX (US) for texas instruments incorporated, Rajen Manicon MURUGAN of Dallas TX (US) for texas instruments incorporated
IPC Code(s): H01L23/64, H01L21/02, H01L21/288, H01L21/3205, H01L21/56, H01L21/768, H01L23/31, H01L23/498, H01L25/16
Abstract: in examples, a semiconductor package comprises a conductive terminal; a semiconductor die including a device side having circuitry formed therein, the device side facing toward the conductive terminal; and a substrate coupled to the conductive terminal and to the device side of the semiconductor die. the substrate includes a first metal layer coupled to first and second vias extending toward and coupled to either the device side of the semiconductor die or the conductive terminal. the substrate includes a second metal layer electrically isolated from the first metal layer by an insulation layer between the first and second metal layers, the second metal layer coupled to a third via extending toward and coupled to either the conductive terminal or the semiconductor die. the first and second metal layers form a marchand balun.
Inventor(s): Rajen M. Murugan of Dallas TX (US) for texas instruments incorporated, Yiqi Tang of Allen TX (US) for texas instruments incorporated, Jie Chen of Plano TX (US) for texas instruments incorporated, Ramlah Abdul Razak of Plano TX (US) for texas instruments incorporated
IPC Code(s): H01L25/16, H01L23/00, H01L23/367, H01L23/552
Abstract: an example semiconductor package comprises a ceramic header having a first open space separated from a second open space by a ceramic barrier. a first heat sink is attached to a bottom of the ceramic header below the first open area. a first integrated circuit (ic) die is mounted on the first heat sink. a second heat sink is attached to a bottom of the ceramic header below the second open area. a second ic die is mounted on the second heat sink. a capacitive interface is disposed in the ceramic barrier between the first ic die and the second ic die. the capacitive has a plurality of capacitive elements alternating with a plurality of shielding elements. the capacitive elements are tunable over a range of capacitive values.
Inventor(s): Tolga DINC of Dallas TX (US) for texas instruments incorporated, Swaminathan SANKARAN of Allen TX (US) for texas instruments incorporated
IPC Code(s): H01P1/185, H01P5/18, H03F3/24
Abstract: a bidirectional phase shifter includes a differential quadrature hybrid coupler, a switch network, and a differential reflection type phase shifter (rtps). the differential quadrature hybrid coupler includes a first phase input/output (i/o) port, an inverse first phase i/o port, a second phase i/o port, and an inverse second phase i/o port. the switch network is coupled to the first phase i/o port, the inverse first phase i/o port, the second phase i/o port, and the inverse second phase i/o port. the differential rtps including a differential i/o port coupled to the switch network.
20240072644.CONTROLLER FOR SWITCHING CONVERTERS_simplified_abstract_(texas instruments incorporated)
Inventor(s): Branko MAJMUNOVIC of Dallas TX (US) for texas instruments incorporated, Johan STRYDOM of Saratoga CA (US) for texas instruments incorporated, Brent MCDONALD of Murphy TX (US) for texas instruments incorporated
IPC Code(s): H02M1/38, H02M1/00, H02M3/335
Abstract: a controller circuit is configured to receive a measurement signal representing a power converter state and receive a control signal representing a power converter resonant period. based on the power converter state and the power converter resonant period, the controller circuit determines for a switching cycle: a charging interval, a first dead time interval, a discharging interval, and a second dead time interval. the first dead time interval is after the charging interval. the discharging interval is after the first dead time interval. the second dead time interval is after the discharging interval. the controller circuit provides a first drive signal and a second drive signal based on the charging interval, the first dead time interval, the discharging interval, and the second dead time interval.
20240072652.COMMON MODE EMI FILTER_simplified_abstract_(texas instruments incorporated)
Inventor(s): Yogesh Ramadass of SAN JOSE CA (US) for texas instruments incorporated, Ashish Kumar of SANTA CLARA CA (US) for texas instruments incorporated
IPC Code(s): H02M1/44, H02M1/12, H02M1/15
Abstract: described embodiments include a circuit for filtering electromagnetic interference (emi) that includes an electrically conductive housing enclosing the circuit, a first power terminal providing a first signal, and a second power terminal providing a second signal, the first and second signals forming a differential power input. a filter circuit provides a common mode noise cancelling signal at an output responsive to first and second inputs. an inductive choke has first and second coils that are magnetically coupled. the first coil is coupled between the first power terminal and a first converter input. the second coil is coupled between the second power terminal and a second converter input. a third capacitor is coupled between the filter output and the second power terminal. a fourth capacitor is coupled between the first power terminal and the second power terminal, and an inductor is coupled between the housing and a ground terminal.
Inventor(s): Liang Zhang of Beijing (CN) for texas instruments incorporated
IPC Code(s): H02M3/158, H02M3/157
Abstract: a control circuit includes a timeout circuit configured to receive a first control signal. the timeout circuit asserts a timeout output signal on a timeout circuit output responsive to an expiration of a time period following assertion of the first control signal. a counter circuit has an input coupled to the timeout circuit output and has a counter circuit output. responsive to assertion of the first control signal, the counter circuit selectively increments an output count value on the counter circuit output responsive to the timeout output signal having a first logic state or decrements the output count value on the counter circuit output responsive to the timeout output signal having a second logic state. a comparator circuit has a control input coupled to the counter circuit output. the comparator circuit adjusts a magnitude of a reference signal responsive to the output count value from the counter circuit.
Inventor(s): Jose V. FORMENTI of Dallas TX (US) for texas instruments incorporated, Robert MARTINEZ of Lucas TX (US) for texas instruments incorporated, Michael CORRY of Dallas TX (US) for texas instruments incorporated, Sombuddha CHAKRABORTY of Redwood City CA (US) for texas instruments incorporated
IPC Code(s): H02M3/335, H02M1/00, H02M3/00
Abstract: a system includes a control circuit having a voltage input and a control circuit output. the control circuit produces a control voltage at the control circuit output having a magnitude inversely related to a magnitude of an input voltage at the input voltage input. a vco has a vco control input and a vco clock output. the vco control input is coupled to the control circuit output. the vco produces a vco clock on the vco clock output having a frequency that is a function of the control voltage. a protection circuit has a first clock input, a second clock input, and a protection circuit output. the second clock input is coupled to the vco clock output. the protection circuit generates a protection circuit output signal at the protection circuit output based on a difference in frequency between a clock signal at the first clock input and the vco clock.
Inventor(s): Il Han Kim of Allen TX (US) for texas instruments incorporated, Xiaolin Lu of Plano TX (US) for texas instruments incorporated
IPC Code(s): H02S50/00, H02J3/38, H02J3/46, H02S40/32, H02S40/34
Abstract: a photovoltaic system with an inverter, at least one solar panel for providing electrical power, and electrical wiring for coupling electrical power from the at least one solar panel to the inverter. also included is a transmitter for transmitting a messaging protocol along the electrical wiring, where the protocol includes a multibit wireline signal. also included is circuitry for selectively connecting the electrical power from the at least one solar panel along the electrical wiring to the inverter in response to the messaging protocol.
Inventor(s): Sravana Kumar GOLI of Bangalore (IN) for texas instruments incorporated, Nagesh SURENDRANATH of Frisco TX (US) for texas instruments incorporated
IPC Code(s): H03F3/00, H03F3/45
Abstract: in at least one example, a circuit includes an amplifier, a first feedback loop, and a second feedback loop. the amplifier includes an amplifier input and an amplifier output. the first feedback loop includes a first feedback capacitor and a first switch. the first feedback loop is coupled between the amplifier input and the amplifier output. the first feedback capacitor is coupled to the amplifier output through the first switch. the second feedback loop includes a second feedback capacitor and a second switch. the second feedback loop is coupled in parallel with the first feedback loop between the amplifier input and the amplifier output. the second feedback capacitor is coupled to the amplifier input and to the first feedback capacitor through the second switch.
Inventor(s): Shaoping TANG of Allen TX (US) for texas instruments incorporated, Keegan MARTIN of Dallas TX (US) for texas instruments incorporated, Ting-Ta YEN of San Jose CA (US) for texas instruments incorporated
IPC Code(s): H03H9/02, H03H9/17
Abstract: a baw resonator includes first and second electrodes located over a substrate. a piezoelectric layer is located between the first and second electrodes. a guard ring is located between the piezoelectric layer and the second electrode, and is spaced apart from a perimeter of the electrode. the guard ring has a width in a range from 2.5 �m to 3.5 �m.
Inventor(s): Rohan SINHA of Bengaluru (IN) for texas instruments incorporated, Anand KAMRA of Bengaluru (IN) for texas instruments incorporated
IPC Code(s): H03K5/24, H02M3/07, H03K3/037
Abstract: a pulse generator circuit includes a charge pump having a charge pump output. a voltage divider is coupled to the charge pump output. the voltage divider has a voltage divider output. an error amplifier has a first error amplifier input and a second error amplifier input. the first error amplifier input is coupled to the voltage divider output. a dependent current source circuit has a first input coupled to the charge pump output, a second input coupled to the voltage divider output, and a third input coupled to the second error amplifier input. the dependent current source is configured to cause a current to flow from the charge pump output that is proportional to a difference between a first voltage at the voltage divider output and a second voltage at the second error amplifier input.
20240072801.PUSH-PULL BUFFER CIRCUIT_simplified_abstract_(texas instruments incorporated)
Inventor(s): Nghia TANG of Flower Mound TX (US) for texas instruments incorporated
IPC Code(s): H03K19/00, H03F3/26, H03F3/45
Abstract: a buffer circuit includes a first transistor, a second transistor, and a third transistor. the first transistor includes a first current terminal, a second current terminal, and a control terminal. the first current terminal is coupled to a load terminal. the control terminal is coupled to a preamplifier input terminal. the second transistor includes a first current terminal and a second current terminal. the first current terminal of the second transistor is coupled to the second current terminal of the first transistor. the third transistor includes a first current terminal, a second current terminal, and a control terminal. the first current terminal of the third transistor is coupled to the load terminal. the second current terminal of the third transistor is coupled to a ground terminal. the control terminal of the third transistor is coupled to second current terminal of the second transistor.
Inventor(s): Madusudanan Srinivasan Gopalan of ISSAQUAH WA (US) for texas instruments incorporated
IPC Code(s): H03L7/099, H03L7/081, H03L7/085
Abstract: timing alignment circuits for use in synchronizing output signals of high-speed dividers and other clock generators are provided. an example timing alignment circuit includes detection circuitry to receive first and second output signals, and output an error sign signal indicating whether the second output signal leads or lags the first output signal and a divide ratio slip signal. the example timing alignment circuit also includes control and aligning circuitry. the control circuitry receives a first local sync status signal and outputs a first control signal to a first component. the aligning circuitry receives the error sign signal and the divide ratio slip signal from the detection circuitry and also receives a second local sync status signal indicating when the first and second output signals are synchronized. the aligning circuitry outputs a second control signal to a second component that synchronously enables the output path receiving the clocks from different dividers with all rising edges aligned similar to a circuit exiting a synchronous reset.
Inventor(s): Prasanth K of Bangalore (IN) for texas instruments incorporated, Rahul Sharma of Bangalore (IN) for texas instruments incorporated
IPC Code(s): H03M1/06, H03M1/10
Abstract: an example analog-to-digital converter (adc) comprising: sample and hold circuitry coupled to an analog input; a first sub-adc coupled to the sample and hold circuitry; a multiplying digital-to-analog converter (m-dac) coupled to the first sub-adc; summation circuitry coupled to the sample and hold circuitry and the m-dac; an amplifier coupled to the summation circuitry; a second sub-adc coupled to the amplifier; and reference generation circuitry coupled to the first sub-adc, the m-dac, and the second sub-adc, the reference generation circuitry including: reference voltage circuitry coupled to the m-dac; a first resistor coupled to the reference voltage circuitry; a second resistor coupled to the first resistor; and a capacitor coupled in parallel to the second resistor by a switch.
Inventor(s): Vishnu RAVINUTHULA of Dallas TX (US) for texas instruments incorporated
IPC Code(s): H03M1/10
Abstract: a method for calibrating analog-to-digital conversion includes converting, by an analog-to-digital converter (adc), a first input voltage to a first digital code. the first input voltage is generated from a reference voltage used as a reference voltage by the adc. the method includes converting, by the adc, a second input voltage to a second digital code. the second input voltage is generated from the reference voltage used as the reference voltage by the adc. the method also includes calculating a calibration factor based on the first digital code, the second digital code, the first input voltage, and the second input voltage, converting, by the adc, a third voltage to a third digital code, and correcting the third digital code using the calibration factor.
Inventor(s): Sai Aditya Nurani of Bengaluru (IN) for texas instruments incorporated, Rishi Soundararajan of Bangalore (IN) for texas instruments incorporated, Nithin Gopinath of Bangalore (IN) for texas instruments incorporated, Visvesvaraya Pentakota of Bangalore (IN) for texas instruments incorporated, Shagun Dusad of Bangalore (IN) for texas instruments incorporated
IPC Code(s): H03M1/12, H03M1/44, H03M1/50, H03M1/78
Abstract: an analog-to-digital converter circuit incorporating includes a multi-bit input buffer having a differential input and configured to generate, at a plurality of differential outputs, a plurality of residues of a differential input sample relative to a corresponding plurality of zero-crossing references. chopping stages chop the residues, for example with a pseudo-random binary sequence. the circuit further includes zero-crossing comparators, each with differential inputs coupled to receive one of the chopped residues. the zero-crossing comparators are in an ordered sequence of zone thresholds within the input range of the circuit. folding logic circuitry has inputs coupled to outputs of the comparators, and outputs a delay domain signal indicating a magnitude of the one of the residues relative to a nearest zone threshold. digital stage circuitry generates a digital output word representing the received input sample responsive to the comparator outputs and the delay domain signal.
Inventor(s): Michael H. PERROTT of Nashua NH (US) for texas instruments incorporated
IPC Code(s): H03M1/82, H03K19/0185, H03M1/80
Abstract: a digital-to-time converter circuit includes a scrambling and noise shaping circuit, a digital-to-analog converter (dac), and a buffer circuit. the scrambling and noise shaping circuit includes an input and an output. the input is coupled to a delay input terminal. the scrambling and noise shaping circuit is configured to generate a residue value signal that scrambles and noise shapes a mismatch error. the dac includes an input and an output. the input of the dac is coupled to the output of the scrambling and noise shaping circuit. the dac is configured to generate a residue timing signal based on the residue value signal that scrambles and noise shapes the mismatch error. the buffer circuit includes an input and an output. the input of the buffer circuit is coupled to the output of the dac. the output of the buffer circuit is coupled to a signal output terminal.
Inventor(s): Sachin Kalia of Dallas TX (US) for texas instruments incorporated, Tolga Dinc of Dallas TX (US) for texas instruments incorporated, Swaminathan Sankaran of Allen TX (US) for texas instruments incorporated, Sasank Garikapati of Dallas TX (US) for texas instruments incorporated
IPC Code(s): H04B1/525, H04B1/00, H03H7/46, H04L5/14
Abstract: electrical balance duplexers (ebds). an example ebd includes a differential tx port coupled to a first coil, a differential rx port coupled to a second coil, a differential ant port coupled to a third coil, and a differential bal port coupled to a fourth coil. in some cases, the first and second coils are arranged such that magnetic flux cancellation is achieved between the two, thus isolating the tx port from the rx port. in some cases, dc isolation exists between the coils. during operation, the first coil may electromagnetically couple with the third coil and the fourth coil, and the second coil may electromagnetically couple with the third coil and the fourth coil. in some example cases, the first and second coils are each in their own metallization layer, and the third and fourth coils are in the same layer.
Inventor(s): Naveen Kumar KALA of Austin TX (US) for texas instruments incorporated, Ariton XHAFA of Plano TX (US) for texas instruments incorporated, Tariq MUHANNA of Garland TX (US) for texas instruments incorporated, Mathew GIARAMITA of New York NY (US) for texas instruments incorporated
IPC Code(s): H04B1/713, H04L1/16, H04W72/04
Abstract: a method for channel switching by a secondary node. the method includes: receiving, from a primary node, a downlink transmission, measuring one or more statistics about the downlink transmission, determining, from the downlink transmission, an uplink interval, transmitting, to the primary node during the uplink interval, the measured one or more statistics about the downlink transmission, receiving, from the primary node, an indication of a set of useable channels, determining, based on the set of useable channels and at least one of the primary node or the secondary node, a next channel from the set of useable channels, and switching to the next channel based on a switch indication from the primary node.
Inventor(s): Kumaran Vijayasankar of Allen TX (US) for texas instruments incorporated, Ramanuja Vedantham of Allen TX (US) for texas instruments incorporated, Tarkesh Pande of Richardson TX (US) for texas instruments incorporated
IPC Code(s): H04B3/54, H04L12/413
Abstract: systems and methods for setting a carrier-sensing mechanism in a plc node are disclosed. in a plc standard, coexistence is achieved by having the nodes detect a common preamble and backing off by a coexistence interframe space (ceifs) time period to help the node to avoid interfering with the other technologies. in one embodiment, a phy primitive is sent from the phy to the mac know that there has been a preamble detection. a two-level indication may be used—one indication after receiving the preamble and other indication after decoding the entire frame. the mac sets the carrier-sensing mechanism based on the preamble detection.
Inventor(s): Tariq Muhanna of Garland TX (US) for texas instruments incorporated, Ariton Xhafa of Plano TX (US) for texas instruments incorporated, Naveen Kumar Kala of Austin TX (US) for texas instruments incorporated, Mathew Giaramita of New York NY (US) for texas instruments incorporated
IPC Code(s): H04J3/06, H04L12/44
Abstract: a battery management system (bms) is presented herein. the bms has a master node. the master node includes a master transceiver and a controller communicably coupled to the master transceiver. the bms has a plurality (n) of slave nodes. each slave node of the n slave nodes includes a slave transceiver for communicably coupling to at least one battery monitor. the controller of the bms is configured to direct the master transceiver to establish a communications network with the n slave nodes. to establish the communications network, the controller is also configured to respectively assign each of the n slave nodes to non-overlapping time slots of a superframe. the controller is further configured to direct the master transceiver to consecutively receive uplink (ul) transmissions from the n slave nodes in the non-overlapping time slots of the superframe.
Inventor(s): Muralidhar MADABHUSHI BALAJI of Dallas TX (US) for texas instruments incorporated, Terry Alan BARTLETT of Dallas TX (US) for texas instruments incorporated, Jeffrey Matthew KEMPF of Dallas TX (US) for texas instruments incorporated, James Norman HALL of Parker TX (US) for texas instruments incorporated
IPC Code(s): H04N9/31, G02B27/01
Abstract: a device includes at least one processor configured to partition a source image including image components into sub-images, each including a corresponding image component of the image components, and process each sub-image to produce a target image to be projected for each sub-image of the sub-images. the device also includes one or more light sources coupled to the at least one processor and configured to project an incident light, and a phase projection-based display device coupled to the at least one processor and optically coupled to the one or more light sources and configured to modulate, based on the target image of each sub-image, the incident light to separately project the sub-images.
Inventor(s): Yedidya Yechiel VACHNISH of Revava (IL) for texas instruments incorporated, Barak CHERCHES of Ramat Ha'Kovesh (IL) for texas instruments incorporated, Avi Sammy BERKOVICH of Herzeliya (IL) for texas instruments incorporated
IPC Code(s): H04W12/121, H04L9/08, H04L9/30, H04L9/32, H04W12/033
Abstract: in at least one example, a method includes establishing, by a sniffer provisioning server (sps) of a first wireless device, a trusted relationship between the first wireless device and a sniffer tool using a public key of the sniffer tool. an out-of-band (oob) key exchange provisions the public key of the sniffer tool to the wireless device. the method further includes obtaining, by the sps, key material uniquely related to a communication session established between the first wireless device and a second wireless device using a shared password. the key material excludes the shared password and a session key uniquely related to the communication session. the method further includes publishing, by the sps, the key material over a channel to the sniffer tool based on the trusted relationship. the channel is secured using the public key of the sniffer tool.
Inventor(s): Yaron ALPERT of Hod Hasharon (IL) for texas instruments incorporated, Yaniv WEIZMAN of Tel Aviv Jaffa (IL) for texas instruments incorporated, Ariton E. XHAFA of Plano TX (US) for texas instruments incorporated
IPC Code(s): H04W40/32, H04W8/00, H04W40/24
Abstract: in an example, a method includes broadcasting advertising packets from a broadcaster bluetooth device, where the advertising packets include one or more connection parameters for one or more links in a link cluster. the method also includes receiving, at the broadcaster bluetooth device, a link cluster coordination request from a scanner bluetooth device, where the link cluster coordination request includes one or more connection parameters for a link in the link cluster.
Inventor(s): Yaron ALPERT of Hod Hasharon (IL) for texas instruments incorporated, Yaniv WEIZMAN of Tel Aviv Jaffa (IL) for texas instruments incorporated, Ariton E. XHAFA of Plano TX (US) for texas instruments incorporated
IPC Code(s): H04W40/32, H04L1/00, H04W52/02, H04W52/36
Abstract: in an example, a method includes connecting a first bluetooth device to a second bluetooth device via one or more links within a link cluster. the method also includes receiving a request at the first bluetooth device from the second bluetooth device to change one or more link connection parameters of a link within the link cluster. the method includes, responsive to receiving the request, changing the link connection parameter of the link within the link cluster.
Inventor(s): Yaniv WEIZMAN of Tel Aviv (IL) for texas instruments incorporated, Lior GERSI of Kfar Saba (IL) for texas instruments incorporated, Alex BOIANGIU of Ness Ziona (IL) for texas instruments incorporated
IPC Code(s): H04W52/02, H04W4/80
Abstract: a device including a host logic and a wireless controller. the wireless controller includes a transceiver and a scheduler. the scheduler is configured to determine a first device and a second device to cluster together. further, upon occurrence of a communication event, the scheduler is configured to wakeup the transceiver for a period of time for the transceiver to exchange packets with the first and second devices, exchange a packet with the first device, exchange a packet with the second device, and power down the transceiver.
20240073976.MULTI-LINK CHANNEL ASSESSMENT_simplified_abstract_(texas instruments incorporated)
Inventor(s): Yaron ALPERT of Hod Hasharon (IL) for texas instruments incorporated, Yuval MATAR of Hod Hasharon (IL) for texas instruments incorporated
IPC Code(s): H04W76/14, H04W24/08
Abstract: in at least one example, a method includes transmitting, by a first device, probe packets to a second device on multiple links over n transmission opportunities (txops) with synchronous probing transmissions on the multiple links during each txop. n is an integer value greater than 1. each probe packet corresponds to a different set of transmission parameters. each link is established between the first device and the second device over different channels of a wireless transmission medium. the method further includes receiving, by the first device responsive to transmitting the probe packets, feedback from the second device on the multiple links in tandem with the synchronous probing transmissions over the n txops. the method further includes selecting, by the first device, a preferred link from among the multiple links based on the feedback.
Texas Instruments Incorporated patent applications on February 29th, 2024
- Texas Instruments Incorporated
- B81C1/00
- B81B3/00
- G02B26/08
- Texas instruments incorporated
- G01K7/01
- G01R19/00
- H02M1/00
- G01R31/371
- G01R31/396
- H01M10/42
- H04W72/04
- G01R31/382
- G01S13/58
- G01S7/40
- G06F9/30
- G06F21/54
- G09G3/34
- G09G3/00
- G11C17/18
- G11C17/16
- H01L23/525
- H10B20/25
- G11C29/00
- G11C11/418
- H01H1/00
- H01H59/00
- H01P1/12
- H01L21/027
- H01L21/48
- H01L23/498
- H01L21/784
- H01L21/02
- H01L21/3065
- H01L23/50
- H01L21/66
- H01L23/00
- H01L21/56
- H01L23/31
- H01L25/065
- H01L23/64
- H01L21/288
- H01L21/3205
- H01L21/768
- H01L25/16
- H01L23/367
- H01L23/552
- H01P1/185
- H01P5/18
- H03F3/24
- H02M1/38
- H02M3/335
- H02M1/44
- H02M1/12
- H02M1/15
- H02M3/158
- H02M3/157
- H02M3/00
- H02S50/00
- H02J3/38
- H02J3/46
- H02S40/32
- H02S40/34
- H03F3/00
- H03F3/45
- H03H9/02
- H03H9/17
- H03K5/24
- H02M3/07
- H03K3/037
- H03K19/00
- H03F3/26
- H03L7/099
- H03L7/081
- H03L7/085
- H03M1/06
- H03M1/10
- H03M1/12
- H03M1/44
- H03M1/50
- H03M1/78
- H03M1/82
- H03K19/0185
- H03M1/80
- H04B1/525
- H04B1/00
- H03H7/46
- H04L5/14
- H04B1/713
- H04L1/16
- H04B3/54
- H04L12/413
- H04J3/06
- H04L12/44
- H04N9/31
- G02B27/01
- H04W12/121
- H04L9/08
- H04L9/30
- H04L9/32
- H04W12/033
- H04W40/32
- H04W8/00
- H04W40/24
- H04L1/00
- H04W52/02
- H04W52/36
- H04W4/80
- H04W76/14
- H04W24/08
- H01L23/49838
