Texas Instruments Incorporated patent applications on February 1st, 2024
Patent Applications by Texas Instruments Incorporated on February 1st, 2024
Texas Instruments Incorporated: 35 patent applications
Texas Instruments Incorporated has applied for patents in the areas of H01L21/56 (4), H02M1/00 (4), H01L23/16 (4), H01L23/00 (4), H02M1/08 (4)
With keywords such as: circuit, output, data, coupled, signal, semiconductor, configured, input, layer, and having in patent application abstracts.
Patent Applications by Texas Instruments Incorporated
Inventor(s): Jayawardan JANARDHANAN of Bangalore (IN) for texas instruments incorporated, Sandeep RAO of Bangalore (IN) for texas instruments incorporated, Goutam DUTTA of Bangalore (IN) for texas instruments incorporated
IPC Code(s): G01C22/00, G01C21/18, G06F1/16, G01C21/20, G01P15/00, G01C21/16
Abstract: a system for pedestrian use includes an accelerometer having multiple electronic sensors; an electronic circuit operable to generate a signal stream representing magnitude of overall acceleration sensed by the accelerometer, and to electronically correlate a sliding window of the signal stream with itself to produce peaks at least some of which represent walking steps, and further operable to electronically execute a periodicity check to compare different step periods for similarity, and if sufficiently similar then to update a portion of the circuit substantially representing a walking-step count; and an electronic display responsive to the electronic circuit to display information at least in part based on the step count. other systems, electronic circuits and processes are disclosed.
Inventor(s): Vadim Valerievich Ivanov of Tucson AZ (US) for texas instruments incorporated, Srinivas Pulijala of Tucson AZ (US) for texas instruments incorporated, Piyush Kaslikar of Tucson AZ (US) for texas instruments incorporated
IPC Code(s): G01R15/14, G01R19/252
Abstract: a current measurement and control circuit may comprise a shunt resistor coupled between supply and output nodes; a first resistor coupled to the supply node; a second resistor coupled to ground; and a transconductance amplifier having an input coupled to the first resistor to define a compensation node and another input coupled to the output node. the circuit may also include a first transistor having a first current terminal coupled to the compensation node and a second current terminal coupled to the second resistor to define a measurement node; and a second transistor having a first current terminal coupled to ground and a second current terminal coupled to the output node. the circuit may also include an adc having an analog input coupled to the measurement node; an idac having an analog output coupled to the compensation node; and switches to set the circuit in a measurement or a compensation mode.
Inventor(s): VISHAL SHAW of West Bengal (IN) for texas instruments incorporated, PREETAM TADEPARTHY of Bangalore (IN) for texas instruments incorporated, MAYANK JAIN of Bangalore (IN) for texas instruments incorporated, Karthik Anyam of Bangalore (IN) for texas instruments incorporated
IPC Code(s): G06F1/26, H03M7/02, H02M3/04
Abstract: one example includes a vid signal decoder circuit. the circuit includes a coarse resolution decoder that receives a vid signal. the vid signal can be encoded with a digital value of an output voltage. the coarse resolution decoder can decode the vid signal to generate a first digital signal. the circuit also includes a fine resolution decoder that receives the vid signal and to decode the vid signal to generate a second digital signal. the circuit further includes a multiplexer to provide the first digital signal as an output signal responsive to a first state of a selection signal and to provide the second digital signal as the output signal responsive to a second state of the selection signal. the first and second states of the selection signal can be based on a relative amplitude of the first and second digital signals.
Inventor(s): Timothy D. Anderson of University Park TX (US) for texas instruments incorporated
IPC Code(s): G06F3/06
Abstract: a system for handling requests that includes a set of memory banks coupled to a memory controller which comprises a set of read queues, including a read queue currently designated as the priority read queue. the memory controller loads read requests from an associated processor into the set of read queues. to process the read requests, the memory controller is configured to schedule the read requests of the priority read queue based on an availability of the associated memory bank, and if not in the priority read queue, also based on whether the read requests conflict with a recently scheduled read request from the priority read queue. upon an execution of a read request from the priority read queue, the memory controller designates a different one of the set of read queues as the priority read queue, if the read request was at a front of the priority read queue.
Inventor(s): Kumar Desappan of Bangalore (IN) for texas instruments incorporated, Anshu Jain of Bangalore (IN) for texas instruments incorporated, Manu Mathew of Bangalore (IN) for texas instruments incorporated
IPC Code(s): G06F5/01, G06F7/485
Abstract: disclosed herein are systems and methods for determining the scaling factors for a neural network that satisfy the activation functions employed by the nodes of the network. a processor identifies a saturation point of an activation function. next, the processor determines a scaling factor for an output feature map based on the saturation point of the activation function. then, the processor determines a scaling factor for an accumulator based on the scaling for the output feature map and further based on a shift value related to a quantization. finally, the processor determines a scaling factor for a weight map based on the scaling factor for the accumulator.
Inventor(s): Duc Bui of Grand Prairie TX (US) for texas instruments incorporated, Timothy D. Anderson of University Park TX (US) for texas instruments incorporated, Paul Gauvreau of Richardson TX (US) for texas instruments incorporated
IPC Code(s): G06F9/30, G06F9/38
Abstract: disclosed herein are systems and methods for executing multiple instruction set architectures (isas) on a singular processing unit. in an implementation, a processor that includes a first decoder, a second decoder, instruction fetch circuitry, and instruction dispatch circuitry is configured to execute two separate instruction set architectures. in an implementation, the instruction fetch circuitry is configured to fetch instructions from an associated memory. in an implementation the instruction dispatch circuitry is coupled to the instruction fetch circuitry, the first decoder, and the second decoder and is configured to route instructions associated with a first isa to the first decoder, and route instructions associated with a second isa to the second decoder.
20240036867.IMPLIED FENCE ON STREAM OPEN_simplified_abstract_(texas instruments incorporated)
Inventor(s): Naveen BHORIA of Plano TX (US) for texas instruments incorporated, Kai CHIRCA of Dallas TX (US) for texas instruments incorporated, Timothy D. ANDERSON of University Park TX (US) for texas instruments incorporated, Duc BUI of Grand Prairie TX (US) for texas instruments incorporated, Abhijeet A. CHACHAD of Plano TX (US) for texas instruments incorporated, Son Hung TRAN of Murphy TX (US) for texas instruments incorporated
IPC Code(s): G06F9/30, G06F9/38, G06F11/00, G06F12/0897, G06F12/0875, G06F9/32, G06F11/10, G06F9/345
Abstract: techniques related to executing a plurality of instructions by a processor comprising receiving a first instruction configured to cause the processor to output a first data value to a first address in a first data cache, outputting, by the processor, the first data value to a second address in a second data cache, receiving a second instruction configured to cause a streaming engine associated with the processor to prefetch data from the first data cache, determining that the first data value has not been outputted from the second data cache to the first data cache, stalling execution of the second instruction, receiving an indication, from the second data cache, that the first data value has been output from the second data cache to the first data cache, and resuming execution of the second instruction based on the received indication.
Inventor(s): Timothy D. ANDERSON of University Park TX (US) for texas instruments incorporated, Duc BUI of Grand Prairie TX (US) for texas instruments incorporated, Joseph ZBICIAK of San Jose CA (US) for texas instruments incorporated, Reid E. TATGE of Los Altos CA (US) for texas instruments incorporated
IPC Code(s): G06F9/38
Abstract: techniques related to executing a plurality of instructions by a processor comprising a method for executing a plurality of instructions by a processor. the method comprises detecting a pipeline hazard based on one or more instructions provided for execution by an instruction execution pipeline, beginning execution of an instruction, of the one or more instructions on the instruction execution pipeline, stalling a portion of the instruction execution pipeline based on the detected pipeline hazard, storing a register state associated with the execution of the instruction based on the stalling, determining that the pipeline hazard has been resolved, and restoring the register state to the instruction execution pipeline based on the determination.
Inventor(s): Kedar CHITNIS of Bangalore (IN) for texas instruments incorporated, Mihir Narendra MODY of Bangalore (IN) for texas instruments incorporated, Prithvi Shankar YEYYADI ANANTHA of Bangalore (IN) for texas instruments incorporated, Sriramakrishnan GOVINDARAJAN of Bangalore (IN) for texas instruments incorporated, Mohd FAROOQUI of Bangalore (IN) for texas instruments incorporated, Shailesh GHOTGALKAR of Bangalore (IN) for texas instruments incorporated
IPC Code(s): G06F12/02
Abstract: in an example, a method includes storing code for a first central processing unit (cpu) executing a first application in a first region of a memory, and storing code for a second cpu executing a second application in a second region of the memory. the method includes storing shared code for the first cpu and the second cpu in a third region of the memory. the method includes storing read-write data for the first cpu in a fourth region of the memory and storing read-write data for the second cpu in a fifth region of the memory. the method includes translating a first address from a first unique address space for the first cpu to a shared address space in the third region, and translating a second address from a second unique address space for the second cpu to the shared address space in the third region.
20240037180.TRANSIENT CURRENT MANAGEMENT_simplified_abstract_(texas instruments incorporated)
Inventor(s): Donald E. STEISS of Richardson TX (US) for texas instruments incorporated, Timothy ANDERSON of University Park TX (US) for texas instruments incorporated, Francisco A. CANO of Sugar Land TX (US) for texas instruments incorporated, Anthony Martin HILL of Dallas TX (US) for texas instruments incorporated, Kevin P. LAVERY of Sugar Land TX (US) for texas instruments incorporated, Arthur REDFERN of Dallas TX (US) for texas instruments incorporated
IPC Code(s): G06F17/16, G06F7/523
Abstract: in examples, a device comprises control logic configured to detect an idle cycle, an operand generator configured to provide a synthetic operand responsive to the detection of the idle cycle, and a computational circuit. the computational circuit is configured to, during the idle cycle, perform a first computation on the synthetic operand. the computational circuit is configured to, during an active cycle, perform a second computation on an architectural operand.
Inventor(s): Mahesh M. Mehendale of Bangalore (IN) for texas instruments incorporated, Ajit Deepak Gupte of Bangalore (IN) for texas instruments incorporated
IPC Code(s): G06T3/40, H04N19/523, G06T7/238, H04N19/43
Abstract: the architecture shown can perform global search, local search and local sub pixel search in a parallel or in a pipelined mode. all operations are in a streaming mode without the requirement of external intermediate data storage.
Inventor(s): Yi Yan of San Jose CA (US) for texas instruments incorporated, Vivek Arora of San Jose CA (US) for texas instruments incorporated
IPC Code(s): H01F17/00, H01F27/28, H01L23/48, H01L23/64
Abstract: an electronic device with an integrated transformer including a first substrate having a first patterned conductive feature with multiple turns that form a first winding, and a first molded magnetic material that encloses a portion of the first patterned conductive feature, and an adhesive layer on a side of the first substrate. the transformer also includes a second substrate having a second patterned conductive feature with multiple turns that form a second winding, and a second molded magnetic material that encloses a portion of the second patterned conductive feature, the second substrate extending on the adhesive layer to magnetically couple the first and second windings. the electronic device includes a package structure that encloses the first and second substrates.
Inventor(s): Asad Haider of Plano TX (US) for texas instruments incorporated, Hao Yang of Allen TX (US) for texas instruments incorporated, Guruvayurappan Mathur of Allen TX (US) for texas instruments incorporated, Alexei Sadovnikov of Sunnyvale CA (US) for texas instruments incorporated, Abbas Ali of Plano TX (US) for texas instruments incorporated, Umamaheswari Aghoram of Richardson TX (US) for texas instruments incorporated
IPC Code(s): H01L21/762, H01L29/06
Abstract: an electronic device includes a semiconductor substrate and a semiconductor surface layer having a first conductivity type, as well as a buried layer, a deep trench structure and a shallow trench isolation structure, the semiconductor surface layer over the semiconductor substrate and having a top surface, the buried layer having an opposite second conductivity type between the semiconductor surface layer and the semiconductor substrate, the deep trench structure including a trench that extends through the semiconductor surface layer and into the buried layer, a dielectric liner on a sidewall of the trench from the semiconductor surface layer to the buried layer, and polysilicon that extends on the dielectric liner and fills the trench to the side of the semiconductor surface layer, the shallow trench isolation structure extends into the semiconductor surface layer, and the shallow trench isolation structure in contact with the deep trench structure.
Inventor(s): Hao Yang of Allen TX (US) for texas instruments incorporated, Asad Haider of Plano TX (US) for texas instruments incorporated, Guruvayurappan Mathur of Allen TX (US) for texas instruments incorporated, Abbas Ali of Plano TX (US) for texas instruments incorporated, Alexei Sadovnikov of Sunnyvale CA (US) for texas instruments incorporated, Umamaheswari Aghoram of Richardson TX (US) for texas instruments incorporated
IPC Code(s): H01L21/762, H01L29/06
Abstract: an electronic device includes a semiconductor substrate and a semiconductor surface layer having a first conductivity type, the semiconductor surface layer over the semiconductor substrate and having a top surface, a buried layer having an opposite second conductivity type between the semiconductor surface layer and the semiconductor substrate, a dielectric isolation layer that extends over and into the semiconductor surface layer, a deep trench structure that extends through the dielectric isolation layer into the semiconductor surface layer, and a silicide blocking layer on a top surface of the deep trench structure.
Inventor(s): Rafael Jose L. Guevara of ANGELES (PH) for texas instruments incorporated, Christlyn Faith Hobrero Arias of MABALACAT CITY (PH) for texas instruments incorporated
IPC Code(s): H01L23/16, H01L23/31, H01L23/495, H01L23/00, H01L21/56
Abstract: semiconductor packages with cavities and methods of making such semiconductor packages are described. the semiconductor package includes a semiconductor die including an interface region where various components configured to interact with an environment surrounding the package can be located. such components include a humidity sensor, a temperature sensor, a light emitting diode, a solid-state laser, a photodiode, or the like. the semiconductor package includes an opening above the interface region to facilitate proper and adequate operations of the components. the semiconductor package also includes a polymer structure surrounding the interface region, thereby forming the opening. the polymer structure has an uneven inner sidewall profile formed by multiple layers of a polymer material.
Inventor(s): Sreenivasan Kalyani KODURI of Allen TX (US) for texas instruments incorporated, Leslie Edward STARK of Heath TX (US) for texas instruments incorporated
IPC Code(s): H01L23/16, H01L23/31, H01L21/56, H01L23/00
Abstract: in some examples, a semiconductor package comprises a semiconductor die; an operational component on an active surface of the semiconductor die; and a cover coupled to the active surface of the semiconductor die and covering the operational component. the cover comprises a monolithic structure including a vertical portion and a horizontal portion. a hollow area is between the cover and the operational component. the package also includes a mold compound covering the semiconductor die and the cover.
Inventor(s): Woochan Kim of San Jose CA (US) for texas instruments incorporated, Kwang-Soo Kim of Sunnyvale CA (US) for texas instruments incorporated, Vivek Arora of San Jose CA (US) for texas instruments incorporated
IPC Code(s): H01L23/367, H01L23/00, H01L21/48, H01L23/538, H01L23/373
Abstract: an electronic device includes an embedded die frame having a cavity and a routing structure, a semiconductor die in the cavity with a gallium nitride layer on the routing structure, and a heat spreader having a thermally conductive insulator layer and a metal plate, the thermally conductive insulator layer having a first side that faces the embedded die frame and an opposite second side that faces away from the embedded die frame, with a portion of the first side of the thermally conductive insulator layer extending over a side of a silicon substrate of the semiconductor die, and the metal plate on the second side of the thermally conductive insulator layer.
Inventor(s): Vijaylaxmi Gumaste Khanolkar of Pune (IN) for texas instruments incorporated, Anindya Poddar of Sunnyvale CA (US) for texas instruments incorporated, Hassan Omar Ali of Murphy TX (US) for texas instruments incorporated, Dibyajat Mishra of Plano TX (US) for texas instruments incorporated, Venkatesh Srinivasan of Plano TX (US) for texas instruments incorporated, Swaminathan Sankaran of Allen TX (US) for texas instruments incorporated
IPC Code(s): H01L23/66, H01Q1/22, H01L21/56, H01L23/00, H01L23/498
Abstract: in a described example, an apparatus includes: a semiconductor device mounted to a device side surface of a package substrate, the package substrate having a board side surface opposite the device side surface; an antenna module mounted to the package substrate and coupled to the semiconductor device; and mold compound covering the semiconductor device and a portion of the package substrate.
Inventor(s): Raul BLECIC of Freising (DE) for texas instruments incorporated, Giacomo CALABRESE of Freising (DE) for texas instruments incorporated, Sooping SAW of McKinney TX (US) for texas instruments incorporated, Premsagar KITTUR of Richardson TX (US) for texas instruments incorporated
IPC Code(s): H02M1/00, H02M3/24
Abstract: a modulation device may include a variable burst regulator and a current-driven clock generator. the modulation device may include a first output terminal configured to provide a modulated voltage for an operating frequency over a modulation period. the current-driven clock generator may include a second input terminal configured to receive a buffered version of the modulated voltage. the current-driven clock generator may include a second output terminal configured to provide a modulated current during the modulation period. the operating frequency may be proportional to the modulated current. the operating frequency may control the operating frequency over the modulation period.
Inventor(s): Navaneeth Kumar Narayanasamy of Sugarland TX (US) for texas instruments incorporated
IPC Code(s): H02M1/38, H02M1/00, H02M7/5395, H02M1/08
Abstract: a pulse width modulator circuit with circuitry for providing a first and second pulse width modulation signal with dead time periods between the first and second pulse width modulation signals, an input for receiving a signal representative of a current in a load adapted to be driven in response to the first and second pulse width modulation signals, and circuitry coupled to the input for adjusting the dead time periods in response to the signal representative of a current.
20240039402.POWER CONVERTER CONTROL_simplified_abstract_(texas instruments incorporated)
Inventor(s): Naman Bafna of Balaghat (IN) for texas instruments incorporated, Muthusubramanian Venkateswaran of Bangalore (IN) for texas instruments incorporated, Mayank Jain of Ambala Catt (IN) for texas instruments incorporated, Vikram Gakhar of Bangalore (IN) for texas instruments incorporated, Vikas Lakhanpal of Bengaluru (IN) for texas instruments incorporated, Preetam Charan Anand Tadeparthy of Bangalore (IN) for texas instruments incorporated, Pamidi Ramasiddaiah of Bengaluru (IN) for texas instruments incorporated
IPC Code(s): H02M3/155, H03K5/24, H02M1/08
Abstract: in some examples, a circuit includes a state machine. the state machine is configured to operate in a first state in which the state machine gates a pulse width modulation (pwm) signal provided for control of a power converter according to a first signal provided by a voltage control loop. the state machine is configured to operate in a second state in which the state machine gates the pwm signal according to a second signal provided by a current limit comparator. the state machine is configured to transition from the first state to the second state responsive to the second signal being asserted after the first signal is asserted in a switching cycle of the power converter. the state machine is configured to transition from the current state to the first state responsive to the first signal being asserted after the second signal in a switching cycle of the power converter.
Inventor(s): Kae WONG of Allen TX (US) for texas instruments incorporated, Rida ASSAAD of Murphy TX (US) for texas instruments incorporated
IPC Code(s): H02M3/158, H02M1/00
Abstract: a converter includes an inductor and a transistor. a sense circuit couples to the transistor. the sense circuit generates a sense signal responsive to a current through the first transistor. a comparator has first and second comparator inputs and a comparator output. the comparator output controls a signal to the transistor's control input. an error amplifier has an error amplifier input and an error amplifier output coupled to the first comparator input. a slope compensation circuit couples to at least one of the error amplifier output or the sense circuit and generates a slope signal. a peak detection sample/hold (pk-s/h) tracks the slope signal and, responsive to the transistor being turned off, samples the slope signal and provides the sampled slope signal on its output. the pk-s/h output couples to whichever of the error amplifier or sense circuit to which the slope compensation circuit is not coupled.
Inventor(s): Rengang CHEN of Bethlehem PA (US) for texas instruments incorporated, Bo WANG of Easton PA (US) for texas instruments incorporated, Evan REUTZEL of Center Valley PA (US) for texas instruments incorporated, Dattatreya Baragur SURYANARAYANA of Bengaluru (IN) for texas instruments incorporated, Bhaskar RAMACHANDRAN of Bengaluru (IN) for texas instruments incorporated, Preetam TADEPARTHY of Bengaluru (IN) for texas instruments incorporated
IPC Code(s): H02M3/158, H02M1/00
Abstract: a dc-dc converter includes a current sense circuit. the current sense circuit includes a sense current output, an inductor current measurement circuit, an inductor current emulation circuit, a first switch, and a second switch. the inductor current measurement circuit has an output. the inductor current emulation circuit has an output. the first switch is coupled between the output of the inductor current measurement circuit and the sense current output. the second switch is coupled between the output of the inductor current emulation circuit and the sense current output.
20240039475.OSCILLATOR WITH ACTIVE INDUCTOR_simplified_abstract_(texas instruments incorporated)
Inventor(s): Udit RAWAT of West Lafayette IN (US) for texas instruments incorporated, Bichoy BAHR of Allen TX (US) for texas instruments incorporated, Swaminathan SANKARAN of Allen TX (US) for texas instruments incorporated
IPC Code(s): H03B5/24, H03H9/02, G01S13/88
Abstract: an oscillator circuit includes a bulk acoustic wave resonator, a differential active inductor circuit, and a gain circuit. the differential active inductor circuit is configured to bias the bulk acoustic wave resonator. the differential active inductor circuit is coupled between the bulk acoustic wave resonator and a power supply terminal. the gain circuit is coupled to the bulk acoustic wave resonator.
Inventor(s): Hakhamanesh MANSOORZARE of Orlando FL (US) for texas instruments incorporated, Ting-Ta YEN of San Jose CA (US) for texas instruments incorporated, Jeronimo SEGOVIA-FERNANDEZ of San Jose CA (US) for texas instruments incorporated, Bichoy BAHR of Allen TX (US) for texas instruments incorporated
IPC Code(s): H03H3/007, H03H9/10
Abstract: a micro-mechanical resonator die includes: micro-mechanical resonator die layers; a cavity formed in at least one of the micro-mechanical resonator die layers; and a micro-mechanical resonator suspended in the cavity. the micro-mechanical resonator includes: a base; a first resonator portion extending from the base along a first plane; and a second resonator portion extending from the base along a second plane. the first resonator portion is configured to operate in an out-of-plane flexural mode that displaces at least part of the first resonator portion out of the first plane. the second resonator portion is configured to operate in an out-of-plane flexural mode that displaces at least part of the second resonator portion out of the second plane and out-of-phase relative to the first resonator portion.
Inventor(s): Michael Henderson Perrott of NASHUA NH (US) for texas instruments incorporated, Robert Karl Butler of ISSAQUAH WA (US) for texas instruments incorporated
IPC Code(s): H03L7/08, H03L7/107, H03L7/081, H03L7/187, H03L7/04, G11C11/4093, G11C11/4099, H03M1/06, H03M1/08, H03M1/18
Abstract: in described examples, a phase measurement circuit includes a first switch coupled between a power terminal and a phase measurement output, the first switch having a first switch control terminal coupled to an up input. the phase measurement circuit includes a second switch coupled between the phase measurement output, the second switch having a second switch control terminal coupled to a down input. the phase measurement circuit includes a first capacitor coupled between the power terminal and the phase measurement output, a second capacitor coupled between the phase measurement output and a ground terminal, and a charge pump circuit having a first control input, a second control input, and a charge pump output, the first control input coupled to the up input, the second control input coupled to the down input, and the charge pump output coupled to the phase measurement output.
Inventor(s): Ruediger KUHN of Freising (DE) for texas instruments incorporated, Maciej JANKOWSKI of Munich (DE) for texas instruments incorporated
IPC Code(s): H03L7/099
Abstract: in some examples, a circuit includes a phase frequency detector (pfd) having a first input, a second input, and an output. the circuit also includes a control circuit having an input and an output, the control circuit input coupled to the output of the pfd. the circuit also includes a modulation circuit having an input and an output, the modulation circuit input coupled to the output of the control circuit. the circuit also includes an oscillator having an oscillator input and an oscillator output, the oscillator input coupled to the output of the modulation circuit and the output of the oscillator coupled to the second input of the pfd.
Inventor(s): Luke Goetzke of Sahuarita (US) for texas instruments incorporated
IPC Code(s): H03M1/12, G06F7/499
Abstract: a method and circuit for recovering data from a digital bitstream received from an analog to digital converter includes asynchronously oversampling the digital bitstream at a sampling rate dictated by an estimate of a clock rate of the analog to digital converter and a nominal oversampling factor. the method and circuit also includes calculating widths of bits of the digital bitstream, and calculating a learned oversampling factor using the calculated widths of a predetermined number of bits of the digital bitstream and a minimization function. the method and circuit also includes calculating data bits to be inserted to a digital filter for digestion using the calculated widths of the bits of the digital bitstream and the learned oversampling factor.
20240040096.DEFECTIVE PIXEL DETECTION_simplified_abstract_(texas instruments incorporated)
Inventor(s): Jing-Fei Ren of Plano TX (US) for texas instruments incorporated, Hrushikesh Garud of Bangalore (IN) for texas instruments incorporated, Rajasekhar Allu of Plano TX (US) for texas instruments incorporated, Gang Hua of Katy TX (US) for texas instruments incorporated, Niraj Nandan of Plano TX (US) for texas instruments incorporated, Mayank Mangla of Allen TX (US) for texas instruments incorporated, Mihir Narendra Mody of Bangalore (IN) for texas instruments incorporated
IPC Code(s): H04N9/64, G06T7/90, G06T7/00
Abstract: various embodiments disclosed herein relate to defective pixel detection and correction, and more specifically to using threshold functions based on color channels to compare pixel values to threshold values. a method is provided herein that comprises identifying a color channel of an image pixel in a frame and identifying a threshold function based at least on the color channel. the method further comprises applying the threshold function to one or more nearest-neighbor values to obtain a threshold value and determining whether a corresponding sensor pixel is defective based at least on a comparison of the image pixel to the threshold value.
Inventor(s): Hrushikesh Garud of Bangalore (IN) for texas instruments incorporated, Rajasekhar Allu of Plano TX (US) for texas instruments incorporated, Gang Hua of Katy TX (US) for texas instruments incorporated, Jing-Fei Ren of Dallas TX (US) for texas instruments incorporated, Mayank Mangla of Allen TX (US) for texas instruments incorporated, Niraj Nandan of Plano TX (US) for texas instruments incorporated, Mihir Mody of Bangalore (IN) for texas instruments incorporated, Pandy Kalimuthu of Plano TX (US) for texas instruments incorporated
IPC Code(s): H04N23/76, H04N23/11, H04N23/84, H04N23/81
Abstract: a system is provided. the system generally includes a first processor configured to receive image input data from a red-green-blue infrared (rgbir) sensor. the first processor of the system is configured to generate a first intermediate image data from the image input data. the system generally includes a second processor. the second processor of the system is configured to generate a second intermediate image data that includes red-green-blue (rgb) image data from the first intermediate image data, and to generate a third intermediate image data that includes infrared (ir) image data from the first intermediate image data. the system generally includes a third processor. the third processor of the system is configured to process the third intermediate image data. the system generally includes a fourth processor. the fourth processor of the system is configured to process the second image data.
Inventor(s): Hrushikesh Garud of Bangalore (IN) for texas instruments incorporated, Rajasekhar Allu of Plano TX (US) for texas instruments incorporated, Gang Hua of Katy TX (US) for texas instruments incorporated, Pandy Kalimuthu of Plano TX (US) for texas instruments incorporated
IPC Code(s): H04N23/85, H04N23/84, H04N23/11
Abstract: disclosed herein are improvements to pixel pattern conversion, upsampling, and ir decontamination processes. an example includes an image processing pipeline comprising an upstream component, a pattern conversion component downstream with respect to the upstream component in the image processing pipeline, and a downstream component relative to the pattern conversion component. the pattern conversion component is configured to obtain rgb-ir pixel data produced by the upstream component of the image processing pipeline and convert the rgb-ir pixel data into rgb pixel data and ir pixel data using a conversion engine. the conversion engine is configured to demosaic the rgb-ir pixel into the rgb pixel data and the ir pixel data, remosaic the rgb pixel data into an rgb pattern and the ir pixel data into an ir pattern and remove ir contamination from the rgb pixel data of the rgb pattern for use by the downstream component.
Inventor(s): Kumaran VIJAYASANKAR of Allen TX (US) for texas instruments incorporated, Arvind KANDHALU RAGHU of Frisco TX (US) for texas instruments incorporated, Jyothsna KUNDURU of Dallas TX (US) for texas instruments incorporated
IPC Code(s): H04W24/08, H04W16/14
Abstract: in some examples, a device includes receiver circuitry and processing circuitry coupled to the receiver circuitry. in examples, the processing circuitry is configured to transition, at a first time, from monitoring a first channel via the receiver circuitry to monitoring a second channel via the receiver circuitry, wherein the first channel is associated with a first communication protocol and the second channel is associated with a second communication protocol. in examples, the processing circuitry is also configured to transition, at a second time, from monitoring the second channel via the receiver circuitry to monitoring the first channel via the receiver circuitry responsive to not detecting communication on the second channel, wherein an amount of time between the first time and the second time is based on a detection time for the second communication protocol.
Inventor(s): Oran Naftali of Petah Tikva (IL) for texas instruments incorporated, Uri Weinrib of Iod (IL) for texas instruments incorporated, Oren Shani of Kfar Saba (IL) for texas instruments incorporated
IPC Code(s): H04W28/02, H04W52/02, H04W74/00, H04W74/08
Abstract: a wi-fi device in a wlan network includes a processor and a transceiver adapted to be coupled to an antenna, and a power saving medium access in congested network environments algorithm that is activated after a wi-fi connection is established with its access point (ap). a traffic indication map (tim) bitmap in a tim information element received in a beacon frame from the ap is analyzed to determine whether more than a predetermined number of bits (x) are set to indicate the ap has ≥1 buffered frame for ones of the wi-fi devices to conclude whether the wlan is in a congested environment. when in a congested environment, transmissions responsive to the beacon are postponed by entering a sleep mode for a random period of time (p). after p expires, the sleep mode is exited and a poll frame is transmitted to the ap to try to gain medium access.
Inventor(s): ARITON XHAFA of PLANO TX (US) for texas instruments incorporated, JIANWEI ZHOU of ALLEN TX (US) for texas instruments incorporated, XIAOLIN LU of PLANO TX (US) for texas instruments incorporated, IL HAN KIM of ALLEN TX (US) for texas instruments incorporated, KAICHIEN TSAI of ALLEN TX (US) for texas instruments incorporated
IPC Code(s): H04W40/02, H04W36/00, H04L49/201, H04W8/26, H04L12/18, H04W74/08, H04W72/20, H04W72/27, H04W72/30
Abstract: a network includes a mobile network node (mnn) that includes a mobile node communications manager (mncm) to facilitate wireless communications to a plurality of stationary network nodes (snns) in a wireless network via a wireless network protocol. the mncm utilizes a multicast address received over the wireless network. the multicast address is assigned to a predetermined network time slot to communicate uplink data from the mnn to the snns. the mnn receives downlink data via a separate predetermined network address and time slot assigned to a given snn.
20240040783.FLASH MEMORY WITH IREAD TUNING_simplified_abstract_(texas instruments incorporated)
Inventor(s): Toan Tran of Murphy TX (US) for texas instruments incorporated, Stephen A. Keller of Plano TX (US) for texas instruments incorporated
IPC Code(s): H01L27/11521, H01L29/423, H01L29/788, H01L21/28, H01L29/66
Abstract: a flash ic device having icompensation and a method of fabricating the same. responsive to determining a gate pattern misalignment, one or more implant conditions for implanting a dopant may be selected to achieve balanced icharacteristics between adjacent bitcells of the flash ic device.
Texas Instruments Incorporated patent applications on February 1st, 2024
- Texas Instruments Incorporated
- G01C22/00
- G01C21/18
- G06F1/16
- G01C21/20
- G01P15/00
- G01C21/16
- Texas instruments incorporated
- G01R15/14
- G01R19/252
- G06F1/26
- H03M7/02
- H02M3/04
- G06F3/06
- G06F5/01
- G06F7/485
- G06F9/30
- G06F9/38
- G06F11/00
- G06F12/0897
- G06F12/0875
- G06F9/32
- G06F11/10
- G06F9/345
- G06F12/02
- G06F17/16
- G06F7/523
- G06T3/40
- H04N19/523
- G06T7/238
- H04N19/43
- H01F17/00
- H01F27/28
- H01L23/48
- H01L23/64
- H01L21/762
- H01L29/06
- H01L23/16
- H01L23/31
- H01L23/495
- H01L23/00
- H01L21/56
- H01L23/367
- H01L21/48
- H01L23/538
- H01L23/373
- H01L23/66
- H01Q1/22
- H01L23/498
- H02M1/00
- H02M3/24
- H02M1/38
- H02M7/5395
- H02M1/08
- H02M3/155
- H03K5/24
- H02M3/158
- H03B5/24
- H03H9/02
- G01S13/88
- H03H3/007
- H03H9/10
- H03L7/08
- H03L7/107
- H03L7/081
- H03L7/187
- H03L7/04
- G11C11/4093
- G11C11/4099
- H03M1/06
- H03M1/08
- H03M1/18
- H03L7/099
- H03M1/12
- G06F7/499
- H04N9/64
- G06T7/90
- G06T7/00
- H04N23/76
- H04N23/11
- H04N23/84
- H04N23/81
- H04N23/85
- H04W24/08
- H04W16/14
- H04W28/02
- H04W52/02
- H04W74/00
- H04W74/08
- H04W40/02
- H04W36/00
- H04L49/201
- H04W8/26
- H04L12/18
- H04W72/20
- H04W72/27
- H04W72/30
- H01L27/11521
- H01L29/423
- H01L29/788
- H01L21/28
- H01L29/66
