Texas Instruments Incorporated patent applications on December 12th, 2024
Patent Applications by Texas Instruments Incorporated on December 12th, 2024
Texas Instruments Incorporated: 18 patent applications
Texas Instruments Incorporated has applied for patents in the areas of G06F9/345 (2), G06F11/10 (2), G06F9/38 (2), G06F12/0875 (2), G06F9/32 (2) H01L24/13 (2), G01S13/42 (1), H01L23/49541 (1), H04W52/0216 (1), H04N17/002 (1)
With keywords such as: data, signal, coupled, device, having, semiconductor, circuit, input, layer, and based in patent application abstracts.
Patent Applications by Texas Instruments Incorporated
Inventor(s): Sachin Bharadwaj of Bangalore (IN) for texas instruments incorporated, Sriram Murali of Bangalore (IN) for texas instruments incorporated
IPC Code(s): G01S13/42, G01S7/288, G01S13/34, G01S13/58, G01S13/931
CPC Code(s): G01S13/42
Abstract: a multi-mode radar system, radar signal processing methods and instruction-based radar signal processing are provided. in an example, such processing includes using range/mode-specific pushing windows to perform windowing on range and velocity object data before performing an angle transform on the windowed object data matrix to generate a three-dimensional object matrix including range, velocity and angle data. the individual windows have an angular spectral response that corresponds to a combined angular coverage field of view of the transmit and receive antennas for the corresponding mode to minimize the total weighted energy outside the main lobe and to provide increasing spectral leakage outside the combined angular coverage field of view with angular offset from the main lobe to push out much of the spectral leakage into regions where leakage tolerance is high due to the corresponding combined angular coverage field of view of the transmit and receive antennas.
Inventor(s): LEI DING of Plano TX (US) for texas instruments incorporated, Srinath Mathur Ramaswamy of Murphy TX (US) for texas instruments incorporated, Anand Gopalan of Plano TX (US) for texas instruments incorporated, Vaibhav Garg of Plano TX (US) for texas instruments incorporated, Anand Ganesh Dabak of Plano TX (US) for texas instruments incorporated
IPC Code(s): G01S15/10, G01S7/526, G01S15/931
CPC Code(s): G01S15/102
Abstract: in one example, a method comprises using a first transducer, emitting a first acoustic signal representing a first code. the method further comprises using the first transducer, receiving a second acoustic signal, and converting the second acoustic signal to a sensor signal. the method further comprises computing a time-of-flight for the second acoustic signal based on a time difference between when the first transducer emits the first acoustic signal and when the first transducer receives the second acoustic signal. the method further comprises responsive to the correlation result indicating that the third acoustic signal is a reflection of a third acoustic signal emitted by a second transducer: determining a delay time between when the first transducer emits the first acoustic signal and when the second transducer emits the third acoustic signal; adjusting the time-of-flight based on the delay time; and providing a distance measurement based on the adjusted time-of-flight.
Inventor(s): Maneesh Soni of Bangalore (IN) for texas instruments incorporated, Rajeev Suvarna of Bangalore (IN) for texas instruments incorporated, Nikunj Khare of Bangalore (IN) for texas instruments incorporated
IPC Code(s): G06F1/12, G06F13/24
CPC Code(s): G06F1/12
Abstract: disclosed examples include interrupt handling circuitry and methods for managing interrupts of a fast clock domain circuit operated according to a first clock signal by a slow clock domain circuit operated according to a second clock signal in which an interrupt generator circuit generates an interrupt input signal synchronized to the second clock signal, and an interrupt clear circuit selectively resets the interrupt generator circuit in response to an acknowledgment signal from the first circuit asynchronously with respect to the second clock signal.
Inventor(s): Arthur John Redfern of Plano TX (US) for texas instruments incorporated, Asheesh Bhardwaj of Allen TX (US) for texas instruments incorporated
IPC Code(s): G06F3/06, G06F15/00, G06F17/16, G06N3/045
CPC Code(s): G06F3/0647
Abstract: a matrix transfer accelerator (mta) system/method that coordinates data transfers between an external data memory (edm) and a local data memory (ldm) using matrix tiling and/or grouping is disclosed. the system utilizes foreground/background buffering that overlaps compute and data transfer operations and permits edm-to-ldm data transfers with or without zero pad peripheral matrix filling. the system may incorporate an automated zero-fill direct memory access (dma) controller (zdc) that transfers data from the edm to the ldm based on a set of dma controller registers including data width register (dwr), transfer count register (tcr), fill count register (fcr), edm source address register (esr), and ldm target address register (ltr). the zdc transfers matrix data from the edm[esr] to the ldm[ltr] such that edm matrix data of dwr row data width is automatically zero-filled around a periphery of a matrix written to the ldm matrix based on the fcr value.
20240411518. DIVISION AND MODULO OPERATIONS_simplified_abstract_(texas instruments incorporated)
Inventor(s): Dinakar Kondru of Frisco TX (US) for texas instruments incorporated
IPC Code(s): G06F7/535, G06F7/72
CPC Code(s): G06F7/535
Abstract: a device is provided. in some examples, the device includes a division logic circuit having input lines including a first least significant input line. the division logic circuit further includes temporary output lines including a second least significant line. the device also includes a first multiplexer having a first data input coupled to the first least significant input line. the first multiplexer further includes a second data input coupled to the second least significant line.
20240411559. VARIABLE LATENCY INSTRUCTIONS_simplified_abstract_(texas instruments incorporated)
Inventor(s): Timothy D. ANDERSON of University Park TX (US) for texas instruments incorporated
IPC Code(s): G06F9/30, G06F9/32, G06F9/345, G06F9/38, G06F11/00, G06F11/10, G06F12/0875, G06F12/0897
CPC Code(s): G06F9/3016
Abstract: techniques related to executing instructions by a processor comprising receiving a first instruction for execution, determining a first latency value based on an expected amount of time needed for the first instruction to be executed, storing the first latency value in a writeback queue, beginning execution of the first instruction on the instruction execution pipeline, adjusting the latency value based on an amount of time passed since beginning execution of the first instruction, outputting a first result of the first instruction based on the latency value, receiving a second instruction, determining that the second instruction is a variable latency instruction, storing a ready value indicating that a second result of the second instruction is not ready in the writeback queue, beginning execution of the second instruction on the instruction execution pipeline, updating the ready value to indicate that the second result is ready, and outputting the second result.
Inventor(s): Sriramakrishnan Govindarajan of Bangalore (IN) for texas instruments incorporated, Mihir Narendra Mody of Bangalore (IN) for texas instruments incorporated, Prithvi Shankar Yeyyadi Anantha of Bangalore (IN) for texas instruments incorporated, Shailesh Ghotgalkar of Bengaluru (IN) for texas instruments incorporated, Kedar Chitnis of Bangalore (IN) for texas instruments incorporated
IPC Code(s): G06F9/4401, G06F12/14, G06F21/57, G06F21/78, H04L9/32
CPC Code(s): G06F9/4401
Abstract: an example device includes a first interface configured to couple to a first memory that is configured to store an image that includes a set of slices; a second interface configured to couple to a second memory; and a direct memory access circuit coupled to the first and second interfaces. the direct memory access circuit receives a transaction that specifies a read of a slice of the set of slices; and based on the transaction, reads the slice from the first memory; performs operations to the slice; and stores the slice in the second memory.
Inventor(s): Joseph Raymond Michael Zbiciak of Alviso CA (US) for texas instruments incorporated, Jason Lynn Peck of Sugar Land TX (US) for texas instruments incorporated
IPC Code(s): G06F11/36, G06F9/54
CPC Code(s): G06F11/3636
Abstract: devices, streaming engines and functionality are provided for identifying a debug event associated with a data element of a data stream, and performing debugging when a processor executes a software program in connection with the data stream. the debug event is tracked through a data pipeline to the processor. in an embodiment, the debug event is acted on only when the processor is ready to consume the data element associated with the debug event. in an embodiment, the debug event is determined by monitoring iteration counts of loop counters associated with an address generator and comparing the iteration counts to respective stored count values.
Inventor(s): Timothy D. Anderson of University Park TX (US) for texas instruments incorporated, Joseph Zbiciak of San Jose CA (US) for texas instruments incorporated, Duc Quang Bui of Grand Prairie TX (US) for texas instruments incorporated, Abhijeet Chachad of Plano TX (US) for texas instruments incorporated, Kai Chirca of Dallas TX (US) for texas instruments incorporated, Naveen Bhoria of Plano TX (US) for texas instruments incorporated, Matthew D. Pierson of Murphy TX (US) for texas instruments incorporated, Daniel Wu of Plano TX (US) for texas instruments incorporated, Ramakrishnan Venkatasubramanian of Plano TX (US) for texas instruments incorporated
IPC Code(s): G06F12/1045, G06F7/24, G06F7/487, G06F7/499, G06F7/53, G06F7/57, G06F9/30, G06F9/32, G06F9/345, G06F9/38, G06F9/48, G06F11/00, G06F11/10, G06F12/0862, G06F12/0875, G06F12/0897, G06F12/1009, G06F15/78, G06F17/16, H03H17/06
CPC Code(s): G06F12/1045
Abstract: disclosed embodiments include an electronic device having a processor core, a memory, a register, and a data load unit to receive a plurality of data elements stored in the memory in response to an instruction. all of the data elements hare the same data size, which is specified by one or more coding bits. the data load unit includes an address generator to generate addresses corresponding to locations in the memory at which the data elements are located, and a formatting unit to format the data elements. the register is configured to store the formatted data elements, and the processor core is configured to receive the formatted data elements from the register.
Inventor(s): JO BITO of DALLAS TX (US) for texas instruments incorporated, BENJAMIN STASSEN COOK of ADDISON TX (US) for texas instruments incorporated, STEVEN KUMMERL of CARROLLTON TX (US) for texas instruments incorporated
IPC Code(s): H01L23/495, H01L23/498
CPC Code(s): H01L23/49541
Abstract: a packaged semiconductor device includes an ic die having bump features that are coupled to bond pads flip chip attached to a custom lf. the custom lf includes metal structures including metal leads on at least 2 sides, and printed metal providing a printed lf portion including printed metal traces that connect to and extend inward from at least one of the metal leads over the dielectric support material that are coupled to fc pads configured for receiving the bump features including at least some of the printed metal traces coupled to the bond pads on the ic die. the ic die is flip chip mounted on the printed lf portion so that the bump features are connected to the fc pads.
Inventor(s): Rafael Jose Lizares Guevara of Makati City (PH) for texas instruments incorporated, Jose Arvin Matute Plomantes of Dagupan City (PH) for texas instruments incorporated
IPC Code(s): H01L23/00
CPC Code(s): H01L24/13
Abstract: an electronic device includes a semiconductor die having a first side, an orthogonal second side for mounting to a substrate or circuit board, a conductive terminal on the first side, the conductive terminal having a center that is spaced apart from the second side by a first distance along a direction, and a solder structure extending on the conductive terminal, the solder structure having a center that is spaced apart from the center of the conductive terminal by a non-zero second distance along the direction.
Inventor(s): Christopher Daniel MANACK of Flower Mound TX (US) for texas instruments incorporated, Salvatore Frank PAVONE of Murphy TX (US) for texas instruments incorporated, Maricel Fabia ESCAÑO of Angeles City (PH) for texas instruments incorporated, Rafael Jose Lizares GUEVARA of Metro Manila (PH) for texas instruments incorporated
IPC Code(s): H01L23/00
CPC Code(s): H01L24/13
Abstract: in examples, a semiconductor package comprises a semiconductor die having an active surface; a conductive layer coupled to the active surface; and a polyimide layer coupled to the conductive layer. the package also comprises a conductive pillar coupled to the conductive layer and to the polyimide layer; a flux adhesive material coupled to the conductive pillar; and a solder layer coupled to the flux adhesive material. the package further includes a conductive terminal coupled to the solder layer and exposed to a surface of the package, the active surface of the semiconductor die facing the conductive terminal.
20240413239. LDMOS NANOSHEET TRANSISTOR_simplified_abstract_(texas instruments incorporated)
Inventor(s): Henry Litzmann Edwards of Garland TX (US) for texas instruments incorporated, Daniel Pham of Celina TX (US) for texas instruments incorporated, Sujatha Sampath of Salt Lake City UT (US) for texas instruments incorporated, Ali Saadat of Santa Clara CA (US) for texas instruments incorporated, Orlando Lazaro of Cary NC (US) for texas instruments incorporated, Vijay K. Reddy of Plano TX (US) for texas instruments incorporated, Steven Kummerl of Carrollton TX (US) for texas instruments incorporated
IPC Code(s): H01L29/78, H01L29/06, H01L29/08, H01L29/10, H01L29/66
CPC Code(s): H01L29/7813
Abstract: disclosed examples include microelectronic devices, e.g. integrated circuits. one example includes a microelectronic device including a nanosheet lateral drain extended metal oxide semiconductor (ldmos) transistor with source and drain regions having a first conductivity type extending into a semiconductor substrate having an opposite second conductivity type. a superlattice of alternating layers of nanosheets of a channel region and layers of gate conductor are separated by a gate dielectric, the superlattice extending between the source region and the drain region. a drain drift region of the first conductivity type extends under the drain region and a body region of the second type extends around the source region.
Inventor(s): Henry Litzmann Edwards of Garland TX (US) for texas instruments incorporated, Brian Goodlin of Plano TX (US) for texas instruments incorporated, Sujatha Sampath of Salt Lake City UT (US) for texas instruments incorporated
IPC Code(s): H01L29/78, H01L29/06, H01L29/16, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L29/7816
Abstract: a microelectronic device, e.g. an integrated circuit, includes first and second doped semiconductor regions over a semiconductor substrate. a semiconductor nanosheet layer is connected between the first and second semiconductor regions and has a bandgap greater than 1.5 ev. in some examples such a device is implemented as an ldmos transistor. a method of forming the device includes forming a trench in a semiconductor substrate having a first conductivity type. a semiconductor nanosheet stack is formed within the trench, the stack including a semiconductor nanosheet layer and a sacrificial layer. source and drain regions having an opposite second conductivity type are formed extending into the semiconductor nanosheet stack. the sacrificial layer between the source region and the drain region is removed, and the semiconductor nanosheet layer is annealed. a gate dielectric layer is formed on the semiconductor nanosheet layer, and a gate conductor is formed on the gate dielectric layer.
Inventor(s): Shailendra Kumar Baranwal of Murphy TX (US) for texas instruments incorporated, Yogesh Kumar Ramadass of San Jose CA (US) for texas instruments incorporated, Yinglai Xia of Plano TX (US) for texas instruments incorporated
IPC Code(s): H03F3/217, H03F1/02, H04R3/00
CPC Code(s): H03F3/2171
Abstract: described embodiments include an audio amplifier circuit that includes a first amplifier having a differential first amplifier input adapted to be coupled to an audio input source, a multiplexer having first and second mux inputs, a control input and a mux output. the first mux input is coupled to the differential amplifier output. there is a signal generator having a generator input coupled to the mux output. there is also a driver circuit having a driver circuit input and a driver circuit output, the driver circuit input coupled to the generator output, and a second amplifier having a first error input coupled to a current sense terminal that is configured to provide a voltage proportional to a current supplied from a power supply terminal, and a second error input coupled to a current limit terminal configured to provide a reference voltage proportional to a current limit value.
20240414315. FAIL SAFE SURROUND VIEW_simplified_abstract_(texas instruments incorporated)
Inventor(s): Shashank DABRAL of Allen TX (US) for texas instruments incorporated, Aishwarya DUBEY of Plano TX (US) for texas instruments incorporated, Gowtham Abhilash TAMMANA of Irving TX (US) for texas instruments incorporated
IPC Code(s): H04N17/00, G06T1/20, H04N7/18, H04N23/60, H04N23/80, H04N23/90
CPC Code(s): H04N17/002
Abstract: a technique including capturing, by one or more cameras of a set of cameras disposed about a vehicle, one or more images, wherein a surround view system of the vehicle is configured to render a surround view image using a first hardware accelerator based on the one or more images, determining that a first hardware accelerator is unavailable, and rendering the surround view image using a second hardware accelerator based on the captured one or more images.
Inventor(s): Oran Naftali of Petah Tikvah (IL) for texas instruments incorporated, Avi Baum of Giva't Shmuel (IL) for texas instruments incorporated, Yuval Jakira of Tel Aviv (IL) for texas instruments incorporated, Asaf Even-Chen of Rehobot (IL) for texas instruments incorporated
IPC Code(s): H04W52/02, H04L67/12, H04W84/12
CPC Code(s): H04W52/0216
Abstract: a controller is arranged to: receive a first decoded beacon frame which includes a first indication of a first data transmission; receive a second decoded beacon frame which includes a second indication of a second data transmission; compare the first and second decoded beacon frames to determine common bytes in the first and second decoded beacon frames; determine an expected time of receiving the common bytes in a third beacon frame; control a device to enter into a low power mode; and control the device to wake up from the low power mode at a time to receive and decode at least a portion of the third beacon frame, in which the time to wake up is based on the expected time to receive the common bytes instead of based on an expected time to receive a preamble at a start of the third beacon frame.
Inventor(s): Alon Ben Ami of Gedera (IL) for texas instruments incorporated, Shlomit Ben Yakar of Kefar Saba (IL) for texas instruments incorporated, Alon Paycher of Moshav Bait Hanania (IL) for texas instruments incorporated, Uri Weinrib of Sunnyvale CA (US) for texas instruments incorporated
IPC Code(s): E21B7/06
CPC Code(s): H04W72/541
Abstract: system and methods for using channel quality reports to reduce inter-band interference are disclosed. channel information is received at a first wireless communication device from a second wireless communication device. the first wireless device is operating in a first frequency range, and the second wireless device is operating in a second frequency range. the first frequency range is adjacent to the second frequency range. a channel quality report is generated at the first wireless communication device. the channel quality report indicates that particular sub-bands in the first frequency range have low channel quality. the particular sub-bands are selected using the channel information.
Texas Instruments Incorporated patent applications on December 12th, 2024
- Texas Instruments Incorporated
- G01S13/42
- G01S7/288
- G01S13/34
- G01S13/58
- G01S13/931
- CPC G01S13/42
- Texas instruments incorporated
- G01S15/10
- G01S7/526
- G01S15/931
- CPC G01S15/102
- G06F1/12
- G06F13/24
- CPC G06F1/12
- G06F3/06
- G06F15/00
- G06F17/16
- G06N3/045
- CPC G06F3/0647
- G06F7/535
- G06F7/72
- CPC G06F7/535
- G06F9/30
- G06F9/32
- G06F9/345
- G06F9/38
- G06F11/00
- G06F11/10
- G06F12/0875
- G06F12/0897
- CPC G06F9/3016
- G06F9/4401
- G06F12/14
- G06F21/57
- G06F21/78
- H04L9/32
- CPC G06F9/4401
- G06F11/36
- G06F9/54
- CPC G06F11/3636
- G06F12/1045
- G06F7/24
- G06F7/487
- G06F7/499
- G06F7/53
- G06F7/57
- G06F9/48
- G06F12/0862
- G06F12/1009
- G06F15/78
- H03H17/06
- CPC G06F12/1045
- H01L23/495
- H01L23/498
- CPC H01L23/49541
- H01L23/00
- CPC H01L24/13
- H01L29/78
- H01L29/06
- H01L29/08
- H01L29/10
- H01L29/66
- CPC H01L29/7813
- H01L29/16
- H01L29/423
- H01L29/775
- H01L29/786
- CPC H01L29/7816
- H03F3/217
- H03F1/02
- H04R3/00
- CPC H03F3/2171
- H04N17/00
- G06T1/20
- H04N7/18
- H04N23/60
- H04N23/80
- H04N23/90
- CPC H04N17/002
- H04W52/02
- H04L67/12
- H04W84/12
- CPC H04W52/0216
- E21B7/06
- CPC H04W72/541
