Texas Instruments Incorporated patent applications on August 22nd, 2024
Patent Applications by Texas Instruments Incorporated on August 22nd, 2024
Texas Instruments Incorporated: 21 patent applications
Texas Instruments Incorporated has applied for patents in the areas of H01L23/00 (3), H01L29/66 (2), G06F12/0811 (2), H02J7/00 (2), G06F9/30 (2) C25D3/38 (1), H02J9/061 (1), H04L27/2656 (1), H03K19/00346 (1), H03K3/0315 (1)
With keywords such as: terminal, circuit, layer, coupled, output, signal, having, transaction, input, and power in patent application abstracts.
Patent Applications by Texas Instruments Incorporated
Inventor(s): Nazila Dadvand of Richardson TX (US) for texas instruments incorporated
IPC Code(s): C25D3/38, C22C9/04, C25D5/02, C25D5/10, C25D5/50, C25D7/12, H01L23/00
CPC Code(s): C25D3/38
Abstract: a microelectronic device is formed by forming a seed layer that contains primarily zinc. a plating mask is formed over the seed layer, and a copper strike layer is formed on the seed layer using a neutral ph copper plating bath. a main copper layer is formed on the copper strike layer by plating copper on the copper strike layer. the plating mask is subsequently removed. the main copper layer, the copper strike layer, and the seed layer are heated to diffuse copper and zinc, and form a brass layer under the main copper layer, consuming the seed layer between the main copper layer and the substrate. remaining portions of the seed layer are removed by a wet etch process. the main copper layer and the underlying brass layer provide a conductor structure.
Inventor(s): Brett Forejt of Richardson TX (US) for texas instruments incorporated, Hansheng Wang of Carrollton TX (US) for texas instruments incorporated, Noah Robb of Plano TX (US) for texas instruments incorporated
IPC Code(s): G01R31/317
CPC Code(s): G01R31/31727
Abstract: low-frequency oscillator (lfo) monitoring circuits and methods. an example of an lfo monitoring circuit includes a resistor having first and second resistor terminals with the first resistor terminal coupled to a ground terminal, first and second transistors coupled between a supply voltage terminal and the second resistor terminal, the first transistor having a first control terminal and the second transistor having a second control terminal, a ramp generator having first and second outputs coupled to the first and second control terminals, respectively, and first and second inputs configured to receive, respectively, first and second signals representative of a frequency of a low-frequency oscillator, the ramp generator being configured to provide, at the first output, a first ramp signal based on the first signal and, at the second output, a second ramp signal based on the second signal, and a comparator having a comparator input coupled to the second resistor terminal.
20240281231. NESTED LOOP CONTROL_simplified_abstract_(texas instruments incorporated)
Inventor(s): Kai CHIRCA of Dallas TX (US) for texas instruments incorporated, Timothy D. ANDERSON of University Park TX (US) for texas instruments incorporated, Todd T. HAHN of Sugar Land TX (US) for texas instruments incorporated, Alan L. DAVIS of Sugar Land TX (US) for texas instruments incorporated
IPC Code(s): G06F8/41, G06F5/06, G06F9/30
CPC Code(s): G06F8/433
Abstract: a method for compiling and executing a nested loop includes initializing a nested loop controller with an outer loop count value and an inner loop count value. the nested loop controller includes a predicate fifo. the method also includes coalescing the nested loop and, during execution of the coalesced nested loop, causing the nested loop controller to populate the predicate fifo and executing a get predicate instruction having an offset value, where the get predicate returns a value from the predicate fifo specified by the offset value. the method further includes predicating an outer loop instruction on the returned value from the predicate fifo.
20240281278. PIPELINE ARBITRATION_simplified_abstract_(texas instruments incorporated)
Inventor(s): Abhijeet Ashok CHACHAD of Plano TX (US) for texas instruments incorporated, David Matthew THOMPSON of Dallas TX (US) for texas instruments incorporated
IPC Code(s): G06F9/46, G06F9/30, G06F9/38, G06F9/448, G06F9/48, G06F9/54, G06F11/30, G06F12/0804, G06F12/0811, G06F12/0813, G06F12/0817, G06F12/0831, G06F12/0855, G06F12/0871, G06F12/0888, G06F12/0891, G06F12/12, G06F12/121, G06F13/16
CPC Code(s): G06F9/467
Abstract: a method includes receiving, by a first stage in a pipeline, a first transaction from a previous stage in pipeline; in response to first transaction comprising a high priority transaction, processing high priority transaction by sending high priority transaction to a buffer; receiving a second transaction from previous stage; in response to second transaction comprising a low priority transaction, processing low priority transaction by monitoring a full signal from buffer while sending low priority transaction to buffer; in response to full signal asserted and no high priority transaction being available from previous stage, pausing processing of low priority transaction; in response to full signal asserted and a high priority transaction being available from previous stage, stopping processing of low priority transaction and processing high priority transaction; and in response to full signal being de-asserted, processing low priority transaction by sending low priority transaction to buffer.
Inventor(s): Abhijeet Ashok Chachad of Plano TX (US) for texas instruments incorporated, Timothy David Anderson of University Park TX (US) for texas instruments incorporated, David Matthew Thompson of Dallas TX (US) for texas instruments incorporated, Daniel Brad Wu of Plano TX (US) for texas instruments incorporated
IPC Code(s): G06F11/10, G06F3/06, G06F9/38, G06F12/0811, G06F12/0815, G06F12/126, H04W24/10, H04W56/00, H04W72/02, H04W72/044, H04W74/08, H04W74/0833
CPC Code(s): G06F11/1076
Abstract: in described examples, a processor system includes a processor core that generates memory write requests, and a cache memory with a memory controller having a memory pipeline. the cache memory has cache lines of length l. the cache memory has a minimum write length that is less than a cache line length of the cache memory. the memory pipeline determines whether the data payload includes a first chunk and ecc syndrome that correspond to a partial write and are writable by a first cache write operation, and a second chunk and ecc syndrome that correspond to a full write operation that can be performed separately from the first cache write operation. the memory pipeline performs an rmw operation to store the first chunk and ecc syndrome in the cache memory, and performs the full write operation to store the second chunk and ecc syndrome in the cache memory.
20240281394. PROCESSOR EVENT MANAGER_simplified_abstract_(texas instruments incorporated)
Inventor(s): Michael Zwerg of Dallas TX (US) for texas instruments incorporated
IPC Code(s): G06F13/28
CPC Code(s): G06F13/28
Abstract: various embodiments disclosed herein relate to an event manager for handling event notification and acknowledgement between circuits in a computing device. the event manager may be configured with static channels, direct memory access (dma) channels, and dynamically configured channels. each of the channels has conductors that allow a publishing circuit to assert a request signal on a conductor to notify the subscribing circuit of an event and the subscribing circuit to assert an acknowledge signal on a second conductor to notify the publishing circuit of receipt of the request signal. using the request and acknowledge signals, the publishing circuit and subscribing circuit can engage in a 4-way handshake that ensures no events are lost and the events can be communicated reliably across clock domains.
Inventor(s): Jaimal Mallory Williamson of McKinney TX (US) for texas instruments incorporated, Jim C. Lo of Allen TX (US) for texas instruments incorporated
IPC Code(s): H01L23/498, H01L21/48, H01L23/00, H01L23/31
CPC Code(s): H01L23/49894
Abstract: a method of making a multilayer package substrate includes forming a plurality of dielectric layers including a top dielectric layer on a top side and a bottom dielectric layer on a bottom side. a top patterned metal layer is on the top dielectric layer and a bottom patterned metal layer is on the bottom dielectric layer. at least one of the top dielectric layer and the bottom dielectric layer is a porous dielectric layer having a plurality of pores including an average porosity of at least 5% averaged over its thickness.
Inventor(s): John C. Ehmke of Longview TX (US) for texas instruments incorporated, Jennifer Lynne Holm of Dallas TX (US) for texas instruments incorporated
IPC Code(s): H01L23/00, B81B7/00
CPC Code(s): H01L23/562
Abstract: an example apparatus includes a semiconductor device layer including a bond pad area, a bond pad on the semiconductor device layer in the bond pad area; a scribe seal on the semiconductor device layer, the scribe seal surrounding the bond pad on at least three sides; and a swarf barrier on the scribe seal, the swarf barrier including: a first portion a first distance from the semiconductor device layer; and a second portion a second distance from the semiconductor device layer, the second distance being larger than the first distance.
Inventor(s): Henry Litzmann Edwards of Garland TX (US) for texas instruments incorporated, Joseph Maurice Khayat of Bedford NH (US) for texas instruments incorporated, Archana Venugopal of Mountain View CA (US) for texas instruments incorporated
IPC Code(s): H01L29/06, H01L29/66, H01L29/861
CPC Code(s): H01L29/0626
Abstract: an integrated circuit includes a shallow p-type well (spw) below a surface of a semiconductor substrate and a shallow n-type well (snw) below the surface. the spw forms an anode of a diode and the snw forms a cathode of the diode. the snw is spaced apart from the spw by a well space region; and a thin field relief oxide structure lies over the well space region.
Inventor(s): Henry Litzmann Edwards of Garland TX (US) for texas instruments incorporated, Andres Arturo Blanco of Garland TX (US) for texas instruments incorporated, Orlando Lazaro of Cary NC (US) for texas instruments incorporated
IPC Code(s): H01L29/78, H01L29/66
CPC Code(s): H01L29/7826
Abstract: ic apparatus, and manufacturing methods therefor, that include a power transistor and a thermoelectric device. the power transistor is constructed in a plurality of layers formed over a semiconductor substrate. the thermoelectric device is formed in one or more of the plurality of layers and is sensitive to temperature differences within the ic apparatus resulting from operation of the power transistor.
Inventor(s): Yang Wu of Wuhan (CN) for texas instruments incorporated, Yihua Yang of Shanghai (CN) for texas instruments incorporated, Xiaodong Cai of McKinney TX (US) for texas instruments incorporated, Bradford Hunter of Spicewood TX (US) for texas instruments incorporated
IPC Code(s): H02J7/00
CPC Code(s): H02J7/0019
Abstract: described examples include a system having a power source having a first output terminal and a second output terminal and a controller. the system also has a selective charger coupled to the controller, the selective charger configured to couple, in response to instructions from the controller, the first output terminal of the power source to a first node that is configured to be coupled to a first terminal of a selected battery cell of two or more serially coupled battery cells, and couple the second output terminal of the power source to a second node configured to be coupled to a second battery terminal of the selected battery cell.
Inventor(s): Jing Ji of Shanghai (CN) for texas instruments incorporated, Jian Liang of Shanghai (CN) for texas instruments incorporated, Shih-chao Hsu of Shanghai (CN) for texas instruments incorporated, Zejing Wang of Shanghai (CN) for texas instruments incorporated
IPC Code(s): H02J9/06, H02J7/00, H02M3/158
CPC Code(s): H02J9/061
Abstract: a power system includes a transistor device (e.g., one or more nfets) is coupled between input voltage and switching node terminals, to provide a variable sense resistance. the system may further include low-side and high-side switching elements, with the low-side switching element coupled between a ground terminal and the switching node terminal, and the high-side switching element coupled between the switching node terminal and an output voltage terminal. the system may be configured to determine its mode of operation, based on primary and backup battery voltages, and enable a corresponding control loop based on that determined mode. with a control loop enabled, the system may be further configured to control the transistor device to provide a variable sense resistor based on a given control parameter. the low-side switching element may be shared by the modes, and external to a chip that includes the high-side switching element and transistor device.
Inventor(s): Vasishta KIDAMBI of HYDERABAD (IN) for texas instruments incorporated, Harsh PATEL of Mumbai (IN) for texas instruments incorporated, Aalok Dyuti SAHA of BANGALORE (IN) for texas instruments incorporated, Subrato ROY of BANGALORE (IN) for texas instruments incorporated
IPC Code(s): H02M1/08
CPC Code(s): H02M1/08
Abstract: one example includes a testing method that includes connecting a capacitor having a first capacitance to an output terminal of an integrated circuit (ic). the method can also include generating pulse signal responsive to an enable signal provided at at least one input terminal of the ic and providing a drive signal to the output terminal to cause a linearly increasing voltage across the capacitor responsive to the pulse signal. the method can also include measuring a no-load delay. the method can also include measuring the linearly increasing voltage at the output terminal responsive to the drive signal. the method can also include determining a first capacitance charge time for the capacitor responsive to the linearly increasing voltage reaching a threshold and determining a second capacitance charge delay for a second capacitance based on the first capacitance charge time and the no-load delay.
Inventor(s): Timothy Bryan Merkin of Princeton TX (US) for texas instruments incorporated, Orlando Lazaro of Cary NC (US) for texas instruments incorporated, John Russell Broze of Dallas TX (US) for texas instruments incorporated, Nan Xing of Allen TX (US) for texas instruments incorporated
IPC Code(s): H02M1/44, H02M7/217, H03K5/24
CPC Code(s): H02M1/44
Abstract: an apparatus comprises a transmitter circuit having first and second transmit outputs; a rectifier circuit having first and second rectifier inputs and first and second rectifier outputs; an isolation circuit coupled between the first transmit output and the first rectifier input, and between the second transmit output and the second rectifier input; a detector circuit coupled to the rectifier circuit; and a driver circuit having a power terminal, a reference terminal, a driver input, and a driver output, the power terminal coupled to the first rectifier output, the reference terminal coupled to the second rectifier output, and the driver input coupled to an output of the detector circuit.
20240283404. OSCILLATOR WITH ACTIVE INDUCTOR_simplified_abstract_(texas instruments incorporated)
Inventor(s): Udit RAWAT of West Lafayette IN (US) for texas instruments incorporated, Bichoy BAHR of Allen TX (US) for texas instruments incorporated, Swaminathan SANKARAN of Allen TX (US) for texas instruments incorporated
IPC Code(s): H03B5/24, G01S13/88, H03H9/02
CPC Code(s): H03B5/24
Abstract: an apparatus comprises a piezoelectric resonator, a first active inductor circuit, and a second active inductor circuit. the piezoelectric resonator includes a first resonator terminal and a second resonator terminal. the first active inductor circuit is coupled between the first resonator terminal and a power supply terminal, the first active inductor circuit having a first impedance that reduces with a first frequency where the first frequency is at or above 1 ghz. the second active inductor circuit is coupled between the second resonator terminal and the power supply terminal, the second active inductor circuit having a second impedance that reduces with a second frequency where the second frequency is at or above 1 ghz.
Inventor(s): Sravana Kumar Goli of Bangalore (IN) for texas instruments incorporated, Nagesh Surendranath of Plano TX (US) for texas instruments incorporated, Srinivas Bangalore Seshadri of Bangalore (IN) for texas instruments incorporated, Sandeep Kesrimal Oswal of Bangalore (IN) for texas instruments incorporated
IPC Code(s): H03F3/08, G01T1/175, H03L7/093, H03M1/60
CPC Code(s): H03F3/082
Abstract: in described examples, a circuit includes an integrator. the integrator generates a first signal responsive to an input signal. a trigger circuit is coupled to the integrator and receives the first signal. a charge dump circuit is coupled to the integrator and the trigger circuit. the trigger circuit modifies configuration of the charge dump circuit and the integrator when the first signal is greater than a first threshold.
Inventor(s): Subha Sarkar of Bangalore (IN) for texas instruments incorporated, Rajat Agarwal of Bangalore (IN) for texas instruments incorporated, Nagendra Krishnapura of Chennai (IN) for texas instruments incorporated
IPC Code(s): H03H11/04
CPC Code(s): H03H11/04
Abstract: a circuit () includes an active filter (), including an input, a first output, and a second output. the circuit includes a first capacitor () having a first terminal and a second terminal. the first terminal of the first capacitor is coupled to the first output of the active filter, and the second terminal of the first capacitor is coupled to the input of the active filter. the first capacitor has a capacitance value. the circuit includes a capacitor bank () having a first terminal and a second terminal. the first terminal of the capacitor bank is coupled to the second output of the active filter. the second terminal of the capacitor bank is coupled to the second terminal of the first capacitor and coupled to the input of the active filter. the capacitor bank has a capacitance that is equivalent to the capacitance value.
Inventor(s): Vishnu RAVINUTHULA of Dallas TX (US) for texas instruments incorporated, Tianyu Chang of Richardson TX (US) for texas instruments incorporated
IPC Code(s): H03K3/03, H03K3/014, H03K5/135
CPC Code(s): H03K3/0315
Abstract: an oscillator circuit includes a ring oscillator and a ramp generator. the ring oscillator includes a first inverter and a second inverter. the first inverter has and a first inverter input, a first inverter output, and a first power terminal. the second inverter has a second inverter input, a second inverter output, and a second power terminal. the second inverter input is coupled to the first inverter output and the second inverter output is coupled to the first inverter input. the ramp generator circuit has a ramp output coupled to the first power terminal and the second power terminal.
Inventor(s): Deric Wayne Waters of Dallas TX (US) for texas instruments incorporated
IPC Code(s): H03K19/003
CPC Code(s): H03K19/00346
Abstract: an example method includes determining, by a controller of a device, whether a length of transmission data is longer than a threshold and responsive to determining that the length of data is longer than the threshold, setting, by the controller a deglitch duration to a duration. the method also includes transmitting, by the device, the data, while the deglitch duration has the duration.
Inventor(s): Mostafa Sayed Ibrahim of Dallas TX (US) for texas instruments incorporated, Il Han Kim of Allen TX (US) for texas instruments incorporated, Tarkesh Pande of Richardson TX (US) for texas instruments incorporated, Anuj Batra of Dallas TX (US) for texas instruments incorporated
IPC Code(s): H04L27/26, H04B3/54, H04B7/0413, H04L1/1867, H04L5/00, H04L7/04, H04W74/0816
CPC Code(s): H04L27/2656
Abstract: a plc network system and method operative with ofdm for generating mimo frames with suitable preamble portions configured to provide backward compatibility with legacy plc devices and facilitate different receiver tasks such as frame detection and symbol timing, channel estimation and automatic gain control (agc), including robust preamble detection in the presence of impulsive noise and frequency-selective channels of the plc network. a plc device may include a delayed correlation detector and a cross-correlation detector operating in concert to facilitate preamble detection in one implementation.
Inventor(s): Nir Shlomo GROSS of Givhat-Shmuel (IL) for texas instruments incorporated, Israel ZILBERSHMIDET of Netanya (IL) for texas instruments incorporated, Barak CHERCHES of Ramat Ha'Kovesh (IL) for texas instruments incorporated, David LEVY of Kiryat Gat (IL) for texas instruments incorporated
IPC Code(s): H04L47/762, H04L9/40, H04L47/70, H04L47/78, H04L47/80
CPC Code(s): H04L47/762
Abstract: an integrated circuit includes: a processor; a receiver coupled to the processor; and memory coupled to the processor. the memory stores resource coordinator instructions that, when executed by the processor, cause the processor to: maintain a plurality of active secure sessions; identify a priority session trigger; and allocate receiver resources for incoming packets related to the plurality of active secure sessions based on the priority session trigger.
Texas Instruments Incorporated patent applications on August 22nd, 2024
- Texas Instruments Incorporated
- C25D3/38
- C22C9/04
- C25D5/02
- C25D5/10
- C25D5/50
- C25D7/12
- H01L23/00
- CPC C25D3/38
- Texas instruments incorporated
- G01R31/317
- CPC G01R31/31727
- G06F8/41
- G06F5/06
- G06F9/30
- CPC G06F8/433
- G06F9/46
- G06F9/38
- G06F9/448
- G06F9/48
- G06F9/54
- G06F11/30
- G06F12/0804
- G06F12/0811
- G06F12/0813
- G06F12/0817
- G06F12/0831
- G06F12/0855
- G06F12/0871
- G06F12/0888
- G06F12/0891
- G06F12/12
- G06F12/121
- G06F13/16
- CPC G06F9/467
- G06F11/10
- G06F3/06
- G06F12/0815
- G06F12/126
- H04W24/10
- H04W56/00
- H04W72/02
- H04W72/044
- H04W74/08
- H04W74/0833
- CPC G06F11/1076
- G06F13/28
- CPC G06F13/28
- H01L23/498
- H01L21/48
- H01L23/31
- CPC H01L23/49894
- B81B7/00
- CPC H01L23/562
- H01L29/06
- H01L29/66
- H01L29/861
- CPC H01L29/0626
- H01L29/78
- CPC H01L29/7826
- H02J7/00
- CPC H02J7/0019
- H02J9/06
- H02M3/158
- CPC H02J9/061
- H02M1/08
- CPC H02M1/08
- H02M1/44
- H02M7/217
- H03K5/24
- CPC H02M1/44
- H03B5/24
- G01S13/88
- H03H9/02
- CPC H03B5/24
- H03F3/08
- G01T1/175
- H03L7/093
- H03M1/60
- CPC H03F3/082
- H03H11/04
- CPC H03H11/04
- H03K3/03
- H03K3/014
- H03K5/135
- CPC H03K3/0315
- H03K19/003
- CPC H03K19/00346
- H04L27/26
- H04B3/54
- H04B7/0413
- H04L1/1867
- H04L5/00
- H04L7/04
- H04W74/0816
- CPC H04L27/2656
- H04L47/762
- H04L9/40
- H04L47/70
- H04L47/78
- H04L47/80
- CPC H04L47/762
