Texas Instruments Incorporated patent applications on August 1st, 2024
Patent Applications by Texas Instruments Incorporated on August 1st, 2024
Texas Instruments Incorporated: 28 patent applications
Texas Instruments Incorporated has applied for patents in the areas of H01L23/00 (8), H01L23/495 (8), H01L23/31 (8), H01L21/56 (6), H02M3/158 (5) H03K17/0812 (2), G06F12/1045 (1), H01Q13/00 (1), H03M1/1014 (1), H03K19/23 (1)
With keywords such as: die, circuit, coupled, semiconductor, substrate, terminal, control, input, output, and having in patent application abstracts.
Patent Applications by Texas Instruments Incorporated
Inventor(s): Bipin Prasad Heremagalur Ramaprasad of Austin TX (US) for texas instruments incorporated, David Matthew Thompson of Dallas TX (US) for texas instruments incorporated, Abhijeet Ashok Chachad of Plano TX (US) for texas instruments incorporated, Hung Ong of Plano TX (US) for texas instruments incorporated
IPC Code(s): G06F12/1045, G06F15/78
CPC Code(s): G06F12/1045
Abstract: a system comprises a processor including a cpu core, first and second memory caches, and a memory controller subsystem. the memory controller subsystem speculatively determines a hit or miss condition of a virtual address in the first memory cache and speculatively translates the virtual address to a physical address. associated with the hit or miss condition and the physical address, the memory controller subsystem configures a status to a valid state. responsive to receipt of a first indication from the cpu core that no program instructions associated with the virtual address are needed, the memory controller subsystem reconfigures the status to an invalid state and, responsive to receipt of a second indication from the cpu core that a program instruction associated with the virtual address is needed, the memory controller subsystem reconfigures the status back to a valid state.
Inventor(s): Atul Garg of Bangalore (IN) for texas instruments incorporated, Venkatraman Ramakrishnan of Bangalore (IN) for texas instruments incorporated
IPC Code(s): G06F30/398, G06F1/10, G06F30/396
CPC Code(s): G06F30/398
Abstract: a method and computer-implemented system for use with an electronic design automation (eda) tool to optimize clock scheduling. based on an initial timing and area optimized design for a logic circuit, an optimal set of clock anchor points on a clock tree for the logic circuit, and slack statistics for a plurality of elements in the logic circuit, are determined. clock skews for the caps associated with the plurality of elements are then scheduled as a function of the slack statistics. a refined timing and area optimized design for the logic circuit is generated based on the clock skews, and the refined timing and area optimized design is utilized as input to a clock tree synthesis module of the eda tool.
Inventor(s): Chao Zuo of Chengdu (CN) for texas instruments incorporated, Jing Hu of Chengdu (CN) for texas instruments incorporated, Tian Ping Lv of Yibin (CN) for texas instruments incorporated, Abbas Ali of Plano TX (US) for texas instruments incorporated, Manoj K Jain of Plano TX (US) for texas instruments incorporated
IPC Code(s): H01L21/3065
CPC Code(s): H01L21/30655
Abstract: a method of forming an integrated circuit includes forming a plurality of openings in a resist layer over a semiconductor substrate and removing portions of a semiconductor surface layer exposed by the openings, thereby forming a plurality of deep trenches. removing the portions includes performing a first etch loop for a first plurality of repetitions, the first etch loop including a deposition process executed for a first deposition time and an etch process executed for a first etch time. the removing further includes performing a second etch loop for a second plurality of repetitions, the second etch loop including the deposition process executed for a second deposition time and an etch process executed for a second etch time. the second deposition time is at least 10% greater than the first deposition time, and the second etch time is at least 10% greater than the first etch time.
Inventor(s): Yuntao XU of CHENGDU (CN) for texas instruments incorporated, Li Xiang ZHENG of CHENGDU (CN) for texas instruments incorporated, Chin Sern Alex TING of IPOH (MY) for texas instruments incorporated, Chong Han LIM of SELANGOR (MY) for texas instruments incorporated
IPC Code(s): H01L21/48, H01L21/56, H01L23/00, H01L23/31, H01L23/495
CPC Code(s): H01L21/4842
Abstract: one example described herein includes a method for fabricating integrated circuit (ic) packages. the method includes providing an incomplete lead frame portion and laser-cutting the incomplete lead frame portion to provide a completed lead frame sheet. the completed lead frame sheet includes through-holes and three-dimensional step features. the method further includes coupling a plurality of ic dies to the completed lead frame sheet and coupling the completed lead frame sheet and the ic dies to packaging material to form an ic package block comprising the ic packages.
Inventor(s): Abbas Ali of Plano TX (US) for texas instruments incorporated, Christopher Scott Whitesell of Garland TX (US) for texas instruments incorporated, John Christopher Shriner of Allen TX (US) for texas instruments incorporated, Henry Litzmann Edwards of Garland TX (US) for texas instruments incorporated
IPC Code(s): H01L21/8234, H01L27/088
CPC Code(s): H01L21/823462
Abstract: a method of fabricating an integrated circuit includes forming a first opening having a first width and a second opening having a second width in a first dielectric layer over a silicon substrate. the openings expose the silicon substrate and the exposed silicon substrate is oxidized to form first and second locos structures having a first thickness. a polysilicon layer is formed over the silicon substrate, so that the polysilicon layer fills the first and second openings. a blanket etch of the polysilicon layer is performed to remove at least a portion of the polysilicon layer over the second locos structure while leaving the first locos structure protected by the polysilicon layer. the silicon substrate under the second locos structure is further oxidized such that the second locos structure has a second thickness greater than the first thickness.
Inventor(s): Bob Lee of New Taipei City (TW) for texas instruments incorporated, Kim Hong Lucas Chai of Dresden (DE) for texas instruments incorporated
IPC Code(s): H01L23/495, H01L21/56, H01L23/00, H01L23/31
CPC Code(s): H01L23/49541
Abstract: a semiconductor package includes a metallic substrate, the metallic substrate including a roughened surface, a semiconductor die including bond pads, and an adhesive between the roughened surface of a topside of the metallic substrate and the semiconductor die, therein bonding the semiconductor die to the metallic substrate. the adhesive includes a resin. the metallic substrate further includes a groove about a perimeter of the semiconductor die on the roughened surface, the groove having a surface roughness less than a surface roughness of the roughened surface of the metallic substrate. the groove straddles the topside and a sidewall of the metallic substrate.
Inventor(s): Sreenivasan K. Koduri of Dallas TX (US) for texas instruments incorporated, Ryan Thorpe of Allen TX (US) for texas instruments incorporated, Hank M. Sung of Allen TX (US) for texas instruments incorporated
IPC Code(s): H01L23/495, H01L21/48, H01L23/00, H01L23/31, H10N59/00
CPC Code(s): H01L23/49558
Abstract: an example apparatus includes a metal leadframe that includes: first leads in a first portion; second leads in a second portion spaced from the first leads, the second leads isolated from the first leads; an isolation barrier mounted to a board side surface of the first portion of the metal leadframe; a semiconductor die mounted to the isolation barrier, the semiconductor die having a sensor on a device side surface facing the first portion of the leadframe, the semiconductor die cantilevered and having bond pads on the device side surface exposed in the opening in the metal leadframe; electrical connections coupling the bond pads and second leads in the second portion of the metal leadframe; and mold compound covering the semiconductor die, the electrical connections, the isolation barrier and portions of the first leads and the second leads, the mold compound forming a package body.
Inventor(s): Rajen MURUGAN of DALLAS TX (US) for texas instruments incorporated, Yiqi TANG of ALLEN TX (US) for texas instruments incorporated, Sylvester ANKAMAH-KUSI of DALLAS TX (US) for texas instruments incorporated
IPC Code(s): H01L23/495, H01L21/56, H01L23/00, H01L23/31
CPC Code(s): H01L23/49562
Abstract: a packaged semiconductor device includes a lead frame and a semiconductor die. the semiconductor die has first and second opposing sides, and the first side of the die is mounted to the lead frame. a first set of bond wires and/or bump bonds are configured to electrically couple the die to the lead frame. a passive circuit element is on a substrate, and the substrate is mounted to the second side of the die. a second set of bond wires and/or bump bonds are configured to electrically couple the passive circuit element to the die. a molding material is configured to encapsulate the passive circuit element, the die, and at least a portion of the lead frame.
Inventor(s): Makoto SHIBUYA of Tokyo (JP) for texas instruments incorporated, Kengo AOYA of Beppu-shi Oita-Ken (JP) for texas instruments incorporated
IPC Code(s): H01L23/495, H01L21/56, H01L23/31
CPC Code(s): H01L23/49565
Abstract: an example electronic device includes a substrate having a die pad and a semiconductor device on the die pad electrically connected to the substrate. the device also includes a mold compound over the semiconductor device to provide a packaged electronic device. the packaged electronic device has respective side edges that extend from a first end to terminate in a second end at a distal surface of the mold compound that is spaced apart from the substrate. at least one side edge of the mold compound has a respective surface that is orthogonal to the distal surface and includes a notch extending inwardly from the respective surface.
Inventor(s): Mei Jiao of Chengdu (CN) for texas instruments incorporated, Huo Yun Duan of Chengdu (CN) for texas instruments incorporated, Zi Qi Wang of Chengdu (CN) for texas instruments incorporated, Tiange Xie of Chengdu (CN) for texas instruments incorporated
IPC Code(s): H01L23/495, H01L23/00, H01L23/31
CPC Code(s): H01L23/49575
Abstract: an example apparatus includes: a metal leadframe including a die pad in a central portion and leads spaced from the die pad. the leads include: an interior end spaced from the die pad and having a full thickness of the metal leadframe; a central portion connected to the interior end and extending away from the die pad having a partial thickness less than the full thickness; and an exterior end having the full thickness extending from the central portion. a semiconductor die is mounted to the die pad by die attach material. wire bonds couple bond pads of the semiconductor die to the interior ends of the leads. mold compound covers the semiconductor die, the die pad, the wire bonds, the interior ends of the leads, the central portion of the leads, and portions of the exterior ends of the leads to form a semiconductor device package.
Inventor(s): KWANG-SOO KIM of SUNNYVALE CA (US) for texas instruments incorporated, WOOCHAN KIM of SAN JOSE CA (US) for texas instruments incorporated, VIVEK KISHORECHAND ARORA of SAN JOSE CA (US) for texas instruments incorporated
IPC Code(s): H01L23/552, H01L21/56, H01L23/00, H01L23/31, H01L23/495, H01L23/498
CPC Code(s): H01L23/552
Abstract: an electronic device that includes a substrate and a die disposed on the substrate, the die having an active surface. wire bonds are attached from the active surface of the die to the substrate. a radiation barrier is attached to the substrate and disposed over the die. the radiation barrier is configured to mitigate electromagnetic radiation exposure to the die. a mold compound is formed over the die, the wire bonds, and the radiation barrier.
Inventor(s): Katleen Fajardo TIMBOL of Allen TX (US) for texas instruments incorporated, Rafael Jose Lizares GUEVARA of Angeles (PH) for texas instruments incorporated
IPC Code(s): H01L23/00
CPC Code(s): H01L24/02
Abstract: in some examples, a semiconductor package comprises a semiconductor die including circuitry, a first metal pillar coupled to the circuitry and extending away from the semiconductor die, and a second metal pillar coupled to the circuitry and extending away from the semiconductor die. a distance between the first and second metal pillars does not exceed 100 microns. the package also comprises a polyimide layer covering portions of the first and second metal pillars and covering a region between the first and second metal pillars. the polyimide layer in the region between the first and second metal pillars has a thickness not exceeding 15 microns and lacks a boundary between separate applications of polyimide to the region. the package also includes a mold compound covering the polyimide layer in the region between the first and second metal pillars. the package further includes conductive terminals coupled to the first and second metal pillars and exposed to an exterior of the mold compound.
Inventor(s): Makoto Shibuya of Tokyo (JP) for texas instruments incorporated, Kwang-Soo Kim of Sunnyvale CA (US) for texas instruments incorporated
IPC Code(s): H01L25/16, H01L21/48, H01L21/56, H01L23/00, H01L23/31, H01L23/495
CPC Code(s): H01L25/165
Abstract: in a described example, an apparatus includes: a package substrate with conductive leads; a semiconductor die mounted to the package substrate, the semiconductor die having a first thickness; electrical connections coupling bond pads on the semiconductor die to conductive leads on the package substrate; brackets attached to the package substrate spaced from the semiconductor die and extending away from the package substrate to a distance from the package substrate that is greater than the first thickness of the semiconductor die; and mold compound covering the package substrate, the semiconductor die, the brackets, and the semiconductor die to form a semiconductor device package having a board side surface and a top surface opposite the board side surface, and having portions of the brackets exposed from the mold compound on the top surface of the semiconductor device package to form mounts for a passive component.
Inventor(s): Juan Alejandro Herbsommer of Allen TX (US) for texas instruments incorporated
IPC Code(s): H01Q1/22, H01Q1/36, H01Q1/46, H01Q9/06
CPC Code(s): H01Q1/2283
Abstract: a described example includes: a semiconductor die mounted to a die pad of a package substrate, the semiconductor die having bond pads on a device side surface facing away from the die pad; bond wires coupling the bond pads of the semiconductor die to leads of the package substrate, the leads spaced from the die pad; an antenna positioned over the device side surface of the semiconductor die and having a feed line coupled between the antenna and a device side surface of the semiconductor die; and mold compound covering the semiconductor die, the bond wires, a portion of the leads, and the die side surface of the die pad, a portion of the antenna exposed from the mold compound.
Inventor(s): Yiqi Tang of Allen TX (US) for texas instruments incorporated, Rajen Murugan of Dallas TX (US) for texas instruments incorporated, Harshpreet Bakshi of Dallas TX (US) for texas instruments incorporated
IPC Code(s): H01Q13/00, H01Q1/48, H01Q9/04
CPC Code(s): H01Q13/00
Abstract: a microelectronic package includes a waveguide radiation receiver formed in a first conductor layer of a multilayer package substrate, the multilayer package substrate comprising the first conductor layer spaced from a second conductor layer by a dielectric layer. the microelectronic package further includes a tubular waveguide mounted to the multilayer package substrate such that a central aperture of the tubular waveguide is over the waveguide radiation receiver, and a feed line coupling the waveguide radiation receiver to a transmitter-receiver, the feed line including a conductive via traversing the dielectric layer electrically coupling a first portion of the feed line in the first conductor layer to a second portion of the feed line in the second conductor layer, the first portion adjacent the waveguide radiation receiver, and the second portion adjacent the transmitter-receiver.
20240258811. DISCHARGE CIRCUIT_simplified_abstract_(texas instruments incorporated)
Inventor(s): QIAO YANG of MUENCHEN (DE) for texas instruments incorporated, STEFAN HERZER of MARZLING (DE) for texas instruments incorporated
IPC Code(s): H02J7/00, H02J7/34, H02M3/155
CPC Code(s): H02J7/007
Abstract: a circuit includes a first transistor coupled between a discharge terminal and a ground terminal. the first transistor has a first control terminal. a resistor is coupled between a power terminal and the first control terminal. a second transistor has a second control terminal coupled to the discharge terminal. a rectifying device is coupled between the resistor and the second transistor.
20240258904. PULSED TRANSISTOR DRIVER CIRCUIT_simplified_abstract_(texas instruments incorporated)
Inventor(s): Joseph M Khayat of Bedford NH (US) for texas instruments incorporated
IPC Code(s): H02M1/088, H02M1/00, H02M3/158, H03K17/0812
CPC Code(s): H02M1/088
Abstract: a circuit includes a first drive stage, a second drive stage, and a pulse circuit. the first drive stage is coupled between a drive terminal and high-side transistor control terminal. the second drive stage is coupled between the first drive stage and the high-side transistor control terminal. the pulse circuit is coupled between the high-side transistor control terminal and the second drive stage. the pulse circuit is configured to disable the second drive stage for a pulse interval responsive to a voltage at the high-side transistor control terminal exceeding a threshold voltage.
Inventor(s): Daniel Tennant of Phoenix AZ (US) for texas instruments incorporated, Ahmed E Hashim of Gilbert AZ (US) for texas instruments incorporated
IPC Code(s): H02M3/157, H02M3/158
CPC Code(s): H02M3/157
Abstract: a voltage converter includes a power stage, a compensator circuit, and a modulator circuit. the power stage circuit has an input voltage terminal, an output voltage terminal, and a pulse width modulation (pwm) control input. the compensator circuit has a voltage input coupled to the output voltage terminal and has a compensation output. the modulator circuit has a compensation voltage input and a pwm control output. the compensation voltage input is coupled to the compensation output, and the pwm control output is coupled to the pwm control input. the modulator circuit includes a slope compensation ramp generator circuit that is configured to generate a slope compensation voltage ramp having a slope that decreases during at least a portion of a switching cycle.
20240258917. RINGING CONTROL CIRCUITS_simplified_abstract_(texas instruments incorporated)
Inventor(s): Saqib SATTI of Freising (DE) for texas instruments incorporated, Qiao YANG of Muenchen (DE) for texas instruments incorporated, Stefan HERZER of Marzling (DE) for texas instruments incorporated
IPC Code(s): H02M3/158, H02M1/14, H02M1/32
CPC Code(s): H02M3/158
Abstract: a circuit includes a transistor and a ringing control circuit. the transistor is coupled between an input voltage terminal and a switching terminal. the transistor includes a control terminal. the ringing control circuit has a control input and a control output. the control input is coupled to the switching terminal, and the control output is coupled to the control terminal.
Inventor(s): Yichao TANG of Santa Clara CA (US) for texas instruments incorporated, Jianbo GOU of Spring Valley TX (US) for texas instruments incorporated, Jiana LOU of () for texas instruments incorporated, Duo LI of () for texas instruments incorporated
IPC Code(s): H02M3/158, H02M1/00, H02M3/07, H02M7/483
CPC Code(s): H02M3/1582
Abstract: a boost converter control method includes: obtaining a peak current reference signal; obtaining a current sense signal; obtaining a flying capacitor (c) voltage error feedback signal; and providing switch control signals during a peak current limit mode responsive to the peak current reference signal, the current sense signal, and the cvoltage error feedback signal.
20240258926. ADAPTIVE CLAMP THRESHOLD_simplified_abstract_(texas instruments incorporated)
Inventor(s): Joseph Maurice KHAYAT of Bedford NH (US) for texas instruments incorporated, Wei DA of Manchester NH (US) for texas instruments incorporated
IPC Code(s): H02M3/158, H02M1/00, H02M1/096, H02M1/42
CPC Code(s): H02M3/1584
Abstract: in some examples, an apparatus includes a tuning circuit having a tuning output and first, second, third, fourth, and fifth tuning inputs, wherein the first tuning input is coupled to a sensor input terminal, the second tuning input is coupled to a first sensor threshold terminal, and the third tuning input is coupled to a second sensor threshold terminal, an avalanche diode having a first anode and a first cathode, wherein the first cathode is coupled to a power terminal, and the first anode is coupled to the fourth tuning input, a diode having a second anode and a second cathode, a transistor coupled between the power terminal and the second anode and having a control terminal coupled to the tuning output, and a timeout circuit having a timeout input coupled to the tuning output, and a timeout output coupled to the fifth tuning input.
Inventor(s): Bharath Balaji Kannan of MERRIMACK NH (US) for texas instruments incorporated, Robert Martinez of LUCAS TX (US) for texas instruments incorporated, Jose Antonio Vieira Formenti of ALLEN TX (US) for texas instruments incorporated, Michael Corry of PLANO TX (US) for texas instruments incorporated
IPC Code(s): H02M3/335, B60L53/22, H02M1/08, H02M7/5387, H02P27/06
CPC Code(s): H02M3/335
Abstract: a dc-to-dc converter having primary- and secondary-side circuitry separated by an isolation barrier, with a transformer and a feedback lane across the barrier, uses a dynamic function current source in its secondary-side circuitry to dynamically adjust the hysteresis threshold only at the transformer burst turn-off edge to provide enhanced immunity to transformer switching noise. an output voltage of the converter (or signal based thereon) is compared to the threshold to provide an input to a timing pulse generator that closes a switch to couple the dynamic function current source into voltage threshold setting circuitry. the dynamic function current source can reduce the threshold to a level that avoids chattering in transformer burst turn-off feedback signal caused by the noise, for a duration that can be based on lane delay of the converter and to an amplitude that can be based on the expected maximum negative amplitude of the noise.
Inventor(s): Orlando Lazaro of Cary NC (US) for texas instruments incorporated, Henry Litzmann Edwards of Garland TX (US) for texas instruments incorporated, Andres Arturo Blanco of Garland TX (US) for texas instruments incorporated, Kushal D. Murthy of BANGALORE (IN) for texas instruments incorporated, Ankur Chauhan of KHARAPUR (IN) for texas instruments incorporated
IPC Code(s): H03K3/011, H01L27/02, H03K17/687
CPC Code(s): H03K3/011
Abstract: the present disclosure introduces integrated circuits and related manufacturing methods, wherein each integrated circuit includes an electronic device and a thermoelectric circuit. the electronic device is formed in and/or over a semiconductor substrate. the thermoelectric circuit includes thermopiles formed in and/or over the semiconductor substrate and electrically connected in series. the thermoelectric circuit is configured to modulate operation of the electronic device in response to a potential produced by the plurality of thermopiles.
Inventor(s): Xiaochun Zhao of Dallas TX (US) for texas instruments incorporated, Abidur Rahman of Dallas TX (US) for texas instruments incorporated, Eung Jung Kim of Dallas TX (US) for texas instruments incorporated, Tianhong Yang of Dallas TX (US) for texas instruments incorporated, Huijuan Li of Dallas TX (US) for texas instruments incorporated
IPC Code(s): H03K17/0812
CPC Code(s): H03K17/0812
Abstract: a transistor is coupled between a first voltage input and a voltage output in a first current path. first circuitry is coupled to a second voltage input, a control terminal of the transistor, and the voltage output. second circuitry is coupled between the control terminal and ground in a second current path and between the control terminal and ground in a third current path parallel to the second current path. the second current path includes the control terminal, first and second terminals of the second circuitry, and ground. the third current path includes the control terminal, a second and the third terminal of the second circuitry, and ground. third circuitry is coupled between the control terminal and the voltage output in a fourth current path. the fourth current path includes the control terminal, first and second terminals of the third circuitry, and the voltage output.
20240259011. TEMPERATURE-SENSITIVE SAMPLING_simplified_abstract_(texas instruments incorporated)
Inventor(s): Robert Allan NEIDORFF of Bedford NH (US) for texas instruments incorporated, Robert Kenneth OPPEN of Phoenix AZ (US) for texas instruments incorporated
IPC Code(s): H03K17/0812, G01K7/00, G01R19/10, H03K17/08
CPC Code(s): H03K17/0812
Abstract: in at least one example, an apparatus includes a logic circuit having a switch control output and first and second logic circuit inputs. a pulse generator has a generator output coupled to the first logic circuit input. an elevated temperature detector has a detector output and a temperature sensor. the detector output is coupled between the second logic circuit input and the temperature sensor.
Inventor(s): Timothy Paul Duryea of Dallas TX (US) for texas instruments incorporated
IPC Code(s): H03K19/23, G01R31/317, H03H7/06, H03K3/037
CPC Code(s): H03K19/23
Abstract: described embodiments include a test system having first, second and third circuits having the same design and configured to receive a same input signal. a majority voter circuit has a first voter input coupled to a first circuit output, a second voter input coupled to a second circuit output, a third voter input coupled to a third circuit output, and a voter output. the output signal is equal to a signal present at least two of the voter inputs. a discrepancy detector circuit has first, second and third discrepancy inputs coupled to the first, second and third circuit outputs, respectively. a discrepancy output is configured to: provide a first logic signal responsive to the first, second and third circuit outputs having equal values; and provide a second logic signal responsive to the first, second and third circuit outputs having unequal values.
Inventor(s): Viswanathan NAGARAJAN of Bengaluru (IN) for texas instruments incorporated, Aniket DATTA of Bengaluru (IN) for texas instruments incorporated, Nithin GOPINATH of Bengaluru (IN) for texas instruments incorporated
IPC Code(s): H03M1/10
CPC Code(s): H03M1/1014
Abstract: an analog-to-digital converter (adc) includes: a set of comparators configured to provide comparison results based on an analog signal and respective reference thresholds for comparators of the set of comparators; digitization circuitry configured to provide a digital output code based on the comparison results and a mapping; and calibration circuitry. the calibration circuitry is configured to: receive the comparison results; determine if the analog signal is proximate to one of the respective reference thresholds based on the comparison results; in response to determining the analog signal is proximate to one of the respective reference thresholds, receive adc values based on different pseudorandom binary sequence (prbs) values being applied to the analog signal; determine an offset error based on the adc values; and provide a comparator input offset calibration signal at a calibration circuitry output if the estimated offset error is greater than an offset error threshold.
Inventor(s): Ani Xavier of Bangalore (IN) for texas instruments incorporated, Jagannathan Venkataraman of Bangalore (IN) for texas instruments incorporated
IPC Code(s): H04L7/00
CPC Code(s): H04L7/0008
Abstract: an example system includes: interleaving circuitry including a data input, a plurality of data outputs, and a plurality of clock inputs, the data input coupled to the received data input and each of the plurality of clock inputs coupled to one of the plurality of receiver clock outputs; and handoff circuitry coupled to the interleaving circuitry, the handoff circuitry including: comparison circuitry coupled to the clock generation circuitry and configured to compare the plurality of receiver clocks to the transmission clock; clock configuration circuitry coupled to the comparison circuitry and configured to select one of the plurality of receiver clocks based on the comparison circuitry; and a plurality of flip-flops coupled to the clock configuration circuitry and configured to convert the plurality of data outputs from the plurality of receiver clocks to the transmission clock to generate a plurality of transmission data streams based on the one of the plurality of receiver clocks selected by the clock configuration circuitry.
Texas Instruments Incorporated patent applications on August 1st, 2024
- Texas Instruments Incorporated
- G06F12/1045
- G06F15/78
- CPC G06F12/1045
- Texas instruments incorporated
- G06F30/398
- G06F1/10
- G06F30/396
- CPC G06F30/398
- H01L21/3065
- CPC H01L21/30655
- H01L21/48
- H01L21/56
- H01L23/00
- H01L23/31
- H01L23/495
- CPC H01L21/4842
- H01L21/8234
- H01L27/088
- CPC H01L21/823462
- CPC H01L23/49541
- H10N59/00
- CPC H01L23/49558
- CPC H01L23/49562
- CPC H01L23/49565
- CPC H01L23/49575
- H01L23/552
- H01L23/498
- CPC H01L23/552
- CPC H01L24/02
- H01L25/16
- CPC H01L25/165
- H01Q1/22
- H01Q1/36
- H01Q1/46
- H01Q9/06
- CPC H01Q1/2283
- H01Q13/00
- H01Q1/48
- H01Q9/04
- CPC H01Q13/00
- H02J7/00
- H02J7/34
- H02M3/155
- CPC H02J7/007
- H02M1/088
- H02M1/00
- H02M3/158
- H03K17/0812
- CPC H02M1/088
- H02M3/157
- CPC H02M3/157
- H02M1/14
- H02M1/32
- CPC H02M3/158
- H02M3/07
- H02M7/483
- CPC H02M3/1582
- H02M1/096
- H02M1/42
- CPC H02M3/1584
- H02M3/335
- B60L53/22
- H02M1/08
- H02M7/5387
- H02P27/06
- CPC H02M3/335
- H03K3/011
- H01L27/02
- H03K17/687
- CPC H03K3/011
- CPC H03K17/0812
- G01K7/00
- G01R19/10
- H03K17/08
- H03K19/23
- G01R31/317
- H03H7/06
- H03K3/037
- CPC H03K19/23
- H03M1/10
- CPC H03M1/1014
- H04L7/00
- CPC H04L7/0008
